Using the Power Supply Panel

Using the Power Supply Panel - 2022.2 English

Xilinx Power Estimator User Guide (UG440)

Document ID

UG440

Release Date

2022-10-19

Version

2022.2 English

The Power Supply panel displays the device estimated power across the different supply sources. For example, this information can be used to size or review voltage supply components, such as regulators. The table includes all power required by the internal logic along with power eventually sourced and consumed outside the Xilinx device, such as in external board terminations. This view includes both static and dynamic power.

You can adjust individual voltages within the supported range and XPE will calculate and display the total current required.

Important: When Maximum Process is selected in the Device table and any power-on supply current values exceed the estimated operating current requirements, the Power Supply panel displays the minimum power-on supply requirements, in blue. If any of the current values appear in blue, the total power indicated in the Power Supply panel will not match the Total On-Chip power in the Summary Panel.

Important: For the Maximum Process, the sum of rail-wise power will not match the Total On-Chip power as there are various other factors which affect the currents.

Alert for Maximum Package Current:: This is applicable only for UltraScale+ family including RFSoC and MPSoC devices. The total current cell for VCCINT turns red when the estimated current exceeds the maximum current specification of the selected package.
Multiple power supplies are required to power a Xilinx device. Table 1 presents the voltage source that powers device resources. This table is provided only as a guideline as the available resources vary across the Xilinx device portfolio.

Table 1. FPGA Resources and their Power Supply
Power Supply	Resources Powered
^VCCINT	All CLB resources All routing resources Entire clock tree, including all clock buffers Block RAM/FIFO DSP slices All input buffers Logic elements in the IOB (ILOGIC/OLOGIC) PowerPC™ processor¹ Tri-Mode Ethernet MAC¹ Clock Managers (MMCM, PLL, DCM, etc.)¹ PCIe and PCS portion of MGTs
^VCCBRAM³	Memory array of block RAMs
^VCCO²	All output buffers Some input buffers Input termination Reference resistors to DCI
^VCCAUX ^VCCAUX_IO⁴	Clock Managers (MMCM, PLL, DCM, etc.)(1) IODELAY/IDELAYCTRL All output buffers Differential Input buffers V_REF-based, single-ended I/O standards, for example, HSTL18_I Phaser¹
^MGTAVCC ^MGTAVTT ^MGTVCCAUX ^VCCINT_GT	Analog supply voltages for PMA circuits of transceivers Transceiver termination circuits Quad PLL GTM Core supply
^VCCPINT ^VCCPAUX ^VCCPLL ^VCCO_DDR ^VCCO_MIO	Zynq-7000 SoC: Processor Memory I/O Peripherals AXI Interfaces
^VCC_PSINTFP ^VCC_PSINTLP ^VCC_PSAUX ^VCCPSINTFP_DDR ^VCC_PSPLL ^VPS_MGTRAVCC ^VPS_MGTRAVTT ^VCCO_PSDDR ^VCCO_PSDDR_PLL ^VCCO_PSIO ^VCCINT_VCU	Zynq UltraScale+ MPSoC: Processor Memory I/O Peripherals
^VCCINT_IO	Input buffers in HPIO bank Output buffers in HPIO bank ISERDES/OSERDES IDDR, ODDR IFF, OFF IDELAY, ODELAY BITSLICE - all components HBM HBM AXI Switch HBM MC PHY Clock IO (Read and Write)
These resources are available only in certain device families. Refer to the appropriate data sheets and user guides for more information. ^VCCO in bank 0 (^VCCO_0 or ^VCCO_CONFIG) powers all I/Os in bank 0 as well as the configuration circuitry. See the applicable Configuration User Guide. Xilinx 7 series Block RAM/FIFO only. Xilinx 7 series High Performance (HP) I/O banks only.