Using the Memory Interface Configuration Wizard - 2022.2 English

Xilinx Power Estimator User Guide (UG440)

Document ID
UG440
Release Date
2022-10-19
Version
2022.2 English
For the XPE spreadsheets of 7 Series and later devices, you can enter information for the I/Os involved in the interface between the Xilinx device and external memory by using the Memory Interface Configuration wizard. The Memory Interface Configuration wizard provides a simplified method of filling in the memory interface I/Os in the XPE spreadsheet.

When you configure a memory interface using the wizard, rows are added to the IP Manager sheet, and to the I/O sheet for each output line (for example, Data, Address, and Clock) from the Xilinx device that will be applied to the external memory. The wizard also places rows on the Clock sheet, on the sheet for any clock manager (for example, PLL or MMCM) that is part of the memory interface, and on the Logic sheet. Resources are added representing typical utilization to implement the physical, controller, and user interface layer.

Important: The Memory Interface Configuration wizard does not support all memory interface standards or all interface parameters for the supported standards. The wizard covers many of the common Memory Interface Standards. For a specific standard there could be more pins associated than configured by the wizard. In these cases you might need to modify the output of the wizard or enter the extra pins manually in the I/O sheet for your specific case. Also, if a selection is not available for a specific field, you might be able to manually override the selections in the field. For Better accuracy, create IP in Vivado and generate resource information to manually enter in to XPE.
To add memory interface I/Os to the 7 series and above devices I/O sheet using the Memory Interface Configuration Wizard:
  1. Open the Memory Interface Configuration wizard using one of the following methods:

    On the I/O sheet, click Add Memory Interface button.



    OR

    On the IP Manager Sheet, click Manage IP.



    1. In the IP Manager dialog box, click Create IP.
    2. In the dialog box IP catalog, select Memory Interface.
    3. In the dialog box, click Create.
  2. In the XPE Memory Interface Configuration dialog box, fill out the information in the dialog box for one memory interface in your design.

    The following figure shows the dialog box for UltraScale devices.



    Following are the fields in the XPE Memory Interface Configuration dialog box:

    Standard
    The s wizard supports the following Standards:
    • DDR2
    • DDR3
    • DDR3L
    • DDR4
    • QDR2+
    • RLDRAM2
    • RLDRAM3
    • LPDDR2

    You can also manually enter a memory interface of any other standard in the XPE spreadsheet. For a listing of the supported I/O standards and limits for your specific device, see the appropriate data sheet:

    • Virtex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS183)
    • Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182)
    • Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS181)
    • Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)
    • Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)
    • Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
    • Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923) and Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
    Bank Type
    Select the appropriate bank type, where the choice exists.
    Mem Config (UltraScale devices only)
    Select the appropriate memory configuration.
    Termination (DQ/S)/Input Termination (DQ/S)
    Refers to the DQ (data) and DQS (data strobe) pins. For memory interfaces using the HP banks, use DCI termination as appropriate. For the HR banks, select INTERM_40, INTERM_50, INTERM_60 or external termination (no entry).
    Data Rate
    Enter the target data rate for your memory device.
    Address Width
    The total number of address lines used in the interface, which includes Row, Col, Bank, and, if used, Rank and CS lines.
    Data Width
    Values from 8-144 in increments of 8 are supported, with memory type and device restrictions. Address, data, and control signals must be in the same I/O column so the limit is often lower than 144. Stacked Silicon Interconnect (SSI) technology devices are limited to a width of 72 due to this restriction.
    Read/Write (%)
    Specify the percentage of the time the memory interface is used for reading from and writing to the external memory. The total must be less than or equal to 100% and the interface is assumed to be idle for 100% - (Read% + Write%) of the time. This is reflected in the Output Enable, Term Disable and IBUF Disable percentages.
    Number of Interfaces
    Enter the number of memory interfaces that will use the settings that you are currently entering in the dialog box. When the I/O sheet is populated with the outputs to external memory, the number of pins for each type of line (for example, Address, Data, and Clock lines) will reflect the number of Interfaces you specify.
    Add typical link layer logic (UltraScale devices only)
    Enable this option to automatically populate the resources of the link layer logic for a specific memory interface.
    Module Name
    Allows you to assign a name to the generated configuration. This will help to distinguish multiple configurations on the I/O sheet.
  3. When you have filled out the values for this memory interface, click Create.

    Rows in the I/O sheet will be populated with the information you entered in the dialog box.

  4. For each memory interface in your design, fill out the information in the XPE Memory Interface Configuration dialog box and click Create.

    Each time you click Create rows will be added to the I/O sheet, and to the PHASER block on the Other sheet for 7 series devices.

  5. When you have configured all of the memory interfaces in your design, click Close to close the XPE Memory Interface Configuration dialog box.