Using the Memory Generator Wizard (for Distributed Memory) - 2022.2 English

Xilinx Power Estimator User Guide (UG440)
Document ID
UG440
Release Date
2022-10-19
Version
2022.2 English
In the 7 series/ Zynq®-7000 SoC and UltraScale™ / UltraScale+™ XPE spreadsheets, the Memory Generator wizard allows you to enter distributed memory information in the Logic sheet. You can access the Memory Generator Wizard by clicking the Manage IP button on the Summary sheet or the IP Manager sheet, or the Add Memory button on the Logic sheet. The XPE Memory Generator wizard provides a simplified method of populating the Logic sheet with rows related to distributed memory.

To understand the capabilities of distributed memory and the settings you will enter within XPE, see the UltraScale Architecture Configurable Logic Block User Guide (UG574).

To generate the Logic sheet using the XPE Memory Generator Wizard (the example shown below is from 7 series/Zynq-7000 SoC and later devices):

  1. Open the Memory Generator wizard by doing one of the following:

    On the Logic Sheet, click Add Memory.



    OR

    On the IP Manager Sheet, click Manage IP.



    1. In the IP Manager dialog box, click Create IP.
    2. In the dialog box IP Catalog, select Distributed Memory.
    3. In the dialog box, click Create.
  2. In the Distributed Memory tab of the XPE Memory Generator dialog box, fill out the information in the dialog box for one distributed Memory Type in your design.

    The fields in the Distributed Memory tab are:

    Memory Type
    Select the type of memory your design will use.
    • Single Port RAM
    • Simple Dual Port RAM
    • Single Port ROM
    • Dual Port ROM
    For a description of these memory types, see the UltraScale Architecture Configurable Logic Block User Guide (UG574).
    Clock
    Enter the clock frequency at which the distributed memory will operate. For dual-port memory types, XPE assumes the same clock frequency for both ports.
    Toggle
    Enter the average toggle rate of the data signals. A toggle rate of 50% means that half of the data signals toggle each clock cycle.
    Width
    Enter the bit width for each word in the memory.
    Depth
    Enter the depth of the memory. Width × Depth is the total number of bits in the memory.
    Registered Inputs
    Specify whether the memory inputs will be registered (Registered Inputs selected) or not (Registered Inputs deselected). For a description of input registering, see the UltraScale Architecture Configurable Logic Block User Guide (UG574).
    Registered Outputs
    Specify whether the memory outputs will be registered (Registered Outputs selected) or not (Registered Outputs deselected). For a description of output registering, see the UltraScale Architecture Configurable Logic Block User Guide (UG574).
    Module name
    Allows you to assign a name to the generated distributed memory configuration. This will help to distinguish multiple configurations in the XPE sheets.
  3. When you have filled out the values for this distributed memory, click Create. A row in the Logic sheet will be filled in with the information you entered in the dialog box.
  4. For each distributed memory type in your design, fill out the dialog box and click Create. Each time you click Create a row will be added to the Logic sheet.
  5. When you have configured all of the distributed memory in your design, click Close to close the XPE Memory Generator dialog box.