Training Resources - 2022.2 English

Xilinx Power Estimator User Guide (UG440)

Document ID: UG440
Release Date: 2022-10-19
Version: 2022.2 English

Overview
Introduction
Navigating Content by Design Process
Getting Started with XPE
Opening XPE
User Input Requirements
XPE Calculations and Results
Definitions/Terminology
Supported Device Families
Device Model Accuracy
Advance
Preliminary
Production
Total Power
Device Static Power
Design Static Power
Design Dynamic Power
Activity Rates
Toggle Rates
General guidelines for the toggle-rates of Ex-OR (XOR) circuit
Example
Signal Rates
Fanout
Effective ΘJA (C/W)
ΘSA (C/W)
ΘJB (C/W)
Junction Temperature (°C)
Using XPE User Interface
XPE Cell Color-Coding Scheme
Using the Summary Sheet
Using the Settings Panel
Using the Power Distribution Panels
Using the On-Chip Power Panel
Using the Power Supply Panel
Using the Summary Panel
Using the XPE Toolbar
Import File
Export File
Quick Estimate
Manage IP
Snapshot
Set Default Rates
Reset to Defaults
Using XPE Wizards
Using the Quick Estimate Wizard
Conditions
Environment
Voltage
Design Activity
Design Utilization
Physical Interfaces
Using IP Module Wizards
Using the Memory Generator Wizard (for Distributed Memory)
Using the Memory Generator Wizard (for Block Memory)
Using the Memory Interface Configuration Wizard
Using the Transceiver Configuration Wizard
Using the Add HBM Wizard
Summary
Specifying and Managing Clocks
Specifying Clocks
Using the Clock Management Resource Sheets (DCM, PMCD, PLL, MMCM, Clock Manager)
Using Xilinx Power Estimator Sheets
Overview
Using the Logic Sheet
Memory Generator Wizard and the Logic Sheet (Distributed Memory)
Routing Complexity for UltraScale and UltraScale+ Devices
Using the IP Manager Sheet (7 Series, Zynq-7000 SoC, UltraScale and UltraScale+ Devices)
Creating an IP Module From the IP Manager Sheet
Deleting an IP Module from the IP Manager Sheet
Exporting an IP Module from the IP Manager Sheet
Importing an IP Module Into the IP Manager Sheet
Using an I/O Sheet
Memory Interface Configuration Wizard and the I/O Sheet
Using the Block RAM (BRAM) Sheet
Preliminary Block RAM Estimates
Setting Block RAM Mode for Improved Accuracy
Cascade Block RAM Support for UltraScale Devices
UltraRAM support for UltraScale+ Devices
Memory Generator Wizard and the Block RAM Sheet (Block Memory)
Using the DSP Sheet (MULT, DSP48)
Using the Transceiver Sheets (GTP, GTX, GTH, GTY, GTZ)
Transceiver Operational Modes
Clock Source for Quad-based PLL
Power Down for PLLs
Hard IP Block Support for UltraScale Devices
Transceiver Wizard and the MGT Sheet
GT Power Up / Power Down Sequencing
Using the GTM Sheet
Transceiver Operational Modes
Data Rate and Interface Width
RS-FEC
Using the TEMAC Sheet
Using the PCIe Sheet
Using PPC440 (PowerPC) Sheets
Using the PS Sheet (Zynq-7000 SoC and Zynq UltraScale+ MPSoC)
Using the PS Sheet for Zynq-7000 SoC
Using the PS Sheet for Zynq UltraScale+ MPSoC
Setting Clocks for Zynq UltraScale+ PS Sheet
Example: Setting Petalinux Boot IDLE state
Using Soft-Decision FEC (SD-FEC) Sheet
Mode
Standard
Throughput Utilization
Clock
Using RFADC-DAC Sheet
Estimating HBM Power (HBM Sheet)
HBM in Summary Sheet
Using Other Sheets (7 Series, Zynq-7000 SoC, UltraScale and UltraScale+ Devices)
User Sheet
Exchanging Power Information
Overview
Exporting Settings from XPE to XPower Analyzer
Importing Results from XPower Analyzer
Importing Results from Vivado Power Analysis
Importing and Exporting the Data
Importing Data into XPE
Importing the Existing Xilinx Power Estimator spreadsheet (*.xls)
Importing the Power Estimation Results from ISE or Vivado (*.xpe)
Importing Implementation Results from ISE Map Report (*.mrp)
XPE Import: Project, Confidence Level, and Date
Importing the Power Estimation Results (*.xpe) for UltraScale+ XPE - Power Optimization Status
Exporting XPE Results
Exporting as XPA Settings (*.xpa) File
Exporting as Text Power Report (*.pwr)
Exporting as an XPE Exchange (*.xpe) File
Exporting as an XDC Constraint (*.xdc) File
Automating XPE
Overview
Using Named Cells
Get Available Resource Counts
Get Device Operating Limits
Get and Edit Summary Information
Using Formulas
Using Visual Basic Macros
Scripting XPE
Visual Basic Scripting Example
Perl Scripting Example
Using Snapshots and Graph Sheets
Using the Power Comparison Snapshots Sheet
Adding a Snapshot of the Current Spreadsheet
Importing a Snapshot
Deleting Snapshots from the Power Comparison Snapshots
Using Graph Sheets
On-Chip Power by Function
On-Chip Power over Vccint
Static Current by Supply
On-Chip Typical vs. Maximum Power
On-Chip Power
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Training Resources
Revision History
Please Read: Important Legal Notices

Vivado Design Suite QuickTake Video Tutorial: Using the Xilinx Power Estimator
Vivado Design Suite QuickTake Video: How to Estimate UltraScale Device Power using XPE
Vivado Design Suite QuickTake Video Tutorials

Back to home page