MicroBlaze Processor Embedded Design User Guide (UG1579) - 2022.2 English - UG1579

Document ID: UG1579
Release Date: 2022-11-02
Version: 2022.2 English

Introduction
Device Tools Flow Overview
General Steps for Creating an Embedded Processor Design
Embedded IP Catalog
Making Manual Connections in a Design
Manually Creating and Connecting to I/O Ports
Platform Board Flow in IP Integrator
Memory-Mapping in the Address Editor
Running Design Rule Checks
Integrating a Block Design in the Top-Level Design
Generating Output Products
Creating an HDL Wrapper
Using the Vitis Software Platform
Exporting a Hardware Description
Navigating Content by Design Process
Using a MicroBlaze Processor in an Embedded Design
Creating a MicroBlaze Processor Design
Designing with the MicroBlaze Processor
Using the MicroBlaze Configuration Window
MicroBlaze Configuration Wizard: Welcome Page
Select Processor Implementation
General Settings
MicroBlaze Configuration Wizard: General Page
Instructions
Optimization
Fault Tolerance
MicroBlaze Configuration Wizard: Cache Page
MicroBlaze Configuration Wizard: MMU Page
Memory Management
Memory Management Features
MicroBlaze Configuration Wizard: Debug Page
Debug Options
MicroBlaze Debug Module Interface
Hardware Breakpoints
Interface
Performance Monitoring
Trace and Profiling
MicroBlaze Configuration Wizard: Buses Page
Local Memory Bus Interfaces
AXI and ACE Interfaces
Stream Interfaces
Other Interfaces
MicroBlaze Configuration Wizard: Advanced Mode
MicroBlaze Advanced Mode Exception Tab
Math Exceptions
Bus Exceptions
Other Exceptions
MicroBlaze Advanced Mode Interrupt & Reset Tab
Interrupt
Reset
Vectors
MicroBlaze Advanced Mode PVR Tab
Processor Version Registers
Cross-Trigger Feature of MicroBlaze Processors
Completing Connections
Block Automation
Using Connection Automation
Completing the Design
MicroBlaze Processor Constraints
Taking the Design through Synthesis, Implementation, and Bitstream Generation
Exporting Hardware to the Vitis Integrated Design Environment
Multiple MicroBlaze Processor Designs
Instantiate MicroBlaze IP Cores
Run Connection Automation
Re-Customizing AXI Interconnects
Mapping and Excluding Unwanted Slaves
Designing with the Memory IP Core
Adding the Memory IP
Making Connections with Block Automation
Adding a Clocking Wizard
Adding an AXI Master
Creating a Memory Map
Running Design Rule Checks
Implementing the Design
Reset and Clock Topologies in IP Integrator
MicroBlaze Design without a Memory IP Core
MicroBlaze Design with a Memory IP Core
Designs with Memory IP and the Clocking Wizard
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Training Resources
Revision History
Please Read: Important Legal Notices

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