The PS for Versal architecture integrates a feature-rich 64-bit dual-core Arm Cortex®-A72 (APU) for full power domain and dual-core Arm Cortex®-R5F (RPU) for low power domain. APU PLL is available in the full power domain and generates clocks for Arm Cortex®-A72 core, L2 Cache, FPD Interconnect, and CCI. RPU PLL is available in the low power domain and generates clocks for Arm Cortex®-R5F core, TCM, OCM, and LPD Interconnect.
Note: L2 cache must be enabled when using A72s,
PDM does this automatically and adds power to FPD.
Figure 1. FPD Configuration
Figure 2. LPD Configuration
