All the required power rails for a given device are displayed within the power rail table. The rails are grouped based on their respective power domains (PMC, LPD, FPD, System, PL, and Battery).
Tip: The color shown for each domain matches that of the
power delivery solution as shown in the following figure and it is common across Xilinx
documentation.
Figure 1. Power Design Table
The Power Rails table is divided into the following columns:
- Voltage
- With the exception of VCCO_500, VCCO_501, VCCO_502, and VCCO_503 this column is for reference only. The voltage can only be changed by adjusting the regulator voltage in the Power Supply Design table. For 50x banks, the desired voltage can be selected here.
- Voltage Range (Read Only)
- This column shows the allowed voltage range for each power rail.Tip: It is recommended to keep the voltage at the TYP value, because this means that there is a balanced positive and negative range for the power supply design to cover AC ripple and DC tolerance.
- Step Load
- Step load is the maximum percentage change of the dynamic current on a given
rail.Tip: Only the VCCINT step load can be altered as this impacts the required numbers of decoupling capacitors, the other rails step loads are fixed.
- Current Requirements (Ready Only)
- This is the current requirement for each rail based on the current estimation. It is categorized into Static, Dynamic, Total and Power on Current (A). Power on current is only displayed when Maximum process is set.
- Power Rail Group (Read Only)
- This is the power rail group of the power rail, it is based on the selected power delivery solution. All power rails that are part of the same power rail group are supplied by the same group in the Power Supply Design Table.
- SysMon Reference Voltage
- You can select the SysMon Reference Voltage connection, it is recommended to use the Internal Vref, if the external Vref is used then the required reference voltage needs to be supplied on the PCB.