Power Design Manager Resource Tabs - 2022.2 English

Power Design Manager User Guide (UG1556)

Document ID
Release Date
2022.2 English

After you have entered the required clock for the design, the remaining resources must be estimated. PDM displays the available resources in a tab on the slide view under the Estimation section.

Figure 1. Power Design Manager Resources

Power Tip: For fast navigation, each tab can be expanded using the > icon and you can jump to the desired table by selecting from the displayed list. For example, clicking to select VCU automatically jumps to the PS & VCU tab to display the VCU table.

PDM organizes resources into the following categories:

This shows the Processing Subsystem with the MPSoC Processing Subsystem (PS) which has quad-core Arm® Cortex-A53 and dual-core Arm Cortex®-R5F along with a Mali 400 MP GPU. The Video Codec Unit (VCU) and System Monitors can be configured on this tab. VCU block is only supported for K26 devices for this release of PDM.
As described above, this allows you to enter external and internal clocks as well as the PLL and MMCMs that will be used. All clocks generated on this tab can be selected from the other tabs to ensure the clock fanout and therefore power estimation is accurate.
Voltage & Current Requirements
This table lists all the power rail requirements for the carrier card. Both current and voltage requirements are specified.
Tip: Kria estimation is a departure for a typical power estimation where the MPSoC rails would be displayed. The SOM has a pre-connected power delivery and so PDM simply shows the required inputs. PDM also has DRCs to ensure that the estimated power does not exceed the current limits of the K26 SOM power delivery.
Allows the user to either force the Junction temperature to a fixed value or specify the maximum ambient and effective ThetaJA for the thermal solution (obtained from thermal simulation).
Thermal Loading
This table shows the power dissipated on the device. For Kria, it also shows the other external peripherals such as DDRs, power regulators, and boot devices available on SOM. The values in the thermal loading table must be used as inputs to a third-party thermal simulation.
Figure 2. K26 SOM Flotherm Compact Model

This tab allows you to enter the logic resource usage and toggle rates. The available K26 SOM and supported Versal devices resources and usage are displayed in the usage table.
Figure 3. Logic

Block RAM and URAM
Allows the Block RAM and URAM usage to be entered.
The usage of DSP blocks along with the clock rate and expected toggle rate can be entered here.
The I/O tab, lists all the available interfaces from both the processing subsystem (DDR4, PSMIO, and GTR) and the PL (PL IOs, and GTHs). The Power Summary & Utilization table shows the available interfaces based on the Kria K26 SOM and the 2 x 240 pin connectors to ensure that designs are kept within the K26 SOM limits.
Figure 4. I/O Power Summary and Usage

For the programmable logic (PL) I/Os, the Kria K26 SOM gives access to six banks 3x HD and 3x HP. PDM allows selection of both VCCO voltage for each of these banks as well as the supported I/O standards that correspond to the VCCO voltage selected.

Figure 5. Programmable Logic for IOs

The previous image shows that you can only select 1.8V IOSTANDARDs based on the 1.8V entered for the HDC VCCO. The power estimated for the PL I/Os will also be reflected as a carrier card current and voltage requirement as these VCCOs need to be provided by the user. The VCCO voltage range is also displayed.

Figure 6. Voltage and Current Requirements

Hard Blocks
This tab allows definition of the desired PCIe setup.
Figure 7. PCIe Block Power Estimation