AI Engine - 2022.2 English

Power Design Manager User Guide (UG1556)

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2022.2 English

The AI Engine array introduced in the Xilinx® Versal® architecture caters to solutions for high compute or complex DSP intensive applications, like 5G Wireless or Machine Learning algorithms. AI Engine is a high performance VLIW vector (SIMD) processor with integrated memory and interconnects to help communicate with other AI Engine cores that are connected together in a two dimensional array network in the device.

The AI Engine tab in PDM for Versal ACAP is available for the AI Core Series family and few AI Edge series devices. PDM estimates the power consumption of AI Engine blocks for a particular configuration. The following figure shows the AI Engine Power interface.

Figure 1. AI Engine Power Interface

For an early power estimation, you should provide the configuration details of the AI Engine array such as clock frequency, number of cores, kernel type, and the Vector Load average percentage for the cores. The supported kernel types are Int8, Int16, Int32 and Floating Point.

Tip: When considering the Vector Load percentage, use the average loading percentage. The kernel could be using 100% of the available core run-time, however overhead from pre-fetch, memory accesses, NOPs, stream, and lock stalls should be considered. The recommended range is 30% to 70%.

Data Memory and Interconnect Load fields are auto-populated based on the number of AI Engines used and can be overridden based on the application requirement. There are eight memory banks in an AI Engine tile (each bank is 4 KB in size totaling 32 KB per tile), by default, ODM uses all of them, this can be overridden if the application requires fewer bank accesses.

Memory R/W rate is average Read/Write memory access for each bank.

Tip: The Memory R/W rate is an average value. PDM uses 20% by default. Recommended value range is 10% to 30%.

The AI Engine array interface allows access to rest of the Versal® ACAP, there are interface tiles for both the Programmable Logic (PL) and Network On Chip (NoC), these interfaces tiles are represented as streams. The PL/NoC streams can be overwritten based design application. The interconnect fields are read-only and calculated based on your input. PL streams show the available streams in the first row of AIE tiles and allows you to specify the number of 64b PL streams that are used. It is recommended that PL streams are set at default 14 streams per 20 AIE tiles used. However, PL streams can be changed., You can see a DRC (cell turns yellow in the Utilization tab) when the PL streams exceed the available streams within the total AIE array.

Interconnect load is averaged to a fixed value of 12% and has minimum impact to power and can be overridden by import flow described in the next section. The maximum range for clock speed depends on the speed grade of a device with 1300 MHz for –3H grade. For more information, see Versal ACAP AI Engine Architecture Manual (AM009).