Parameterized Macro: Single Port ROM
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_MEMORY
Introduction
This macro is used to instantiate Single Port ROM. Read operations from the memory can be performed from Port A.
The following describes the basic read and write port usage of an XPM_MEMORY instance.
- All synchronous signals are sensitive to the rising edge of clka, which is assumed to be a buffered and toggling clock signal behaving according to target device and memory primitive requirements.
- A read operation is implicitly performed to address addra combinatorially. The data output is registered each clka cycle that ena is asserted.
- Read data appears on the douta port READ_LATENCY_A CLKA cycles after the associated read operation.
- All read operations are gated by the value of ena on the initiating clka cycle, regardless of input or output latencies.
- For each clka cycle that rsta is asserted, the final output register is immediately but synchronously reset to READ_RESET_VALUE_A, irrespective of READ_LATENCY_A.
- For each clka cycle that regcea is asserted and rsta is de-asserted, the final output register captures and outputs the value from the previous pipeline register.
- Undriven or unknown values provided on module inputs will produce undefined memory array and output port behavior.
- When MEMORY INIT PARAM is used, the maximum supported memory size 4K bits.
- WRITE_MODE_A must be set to “read_first” in Single Port ROM configurations. Violating this will result in a DRC error.
- For better timing performance in larger memories (> 1 Mb), use CASCADE_HEIGHT of 1 with sufficient read latencies.
Note: For larger memories (≥2 MB), the recommended read latency must be > 8 because the
default cascade height used by Vivado synthesis is 8.
Timing Diagrams
Port Descriptions
| Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
|---|---|---|---|---|---|---|
| addra | Input | ADDR_WIDTH_A | clka | NA | Active | Address for port A read operations. |
| clka | Input | 1 | NA | EDGE_RISING | Active | Clock signal for port A. |
| dbiterra | Output | 1 | clka | LEVEL_HIGH | DoNotCare | Leave open. |
| douta | Output | READ_DATA_WIDTH_A | clka | NA | Active | Data output for port A read operations. |
| ena | Input | 1 | clka | LEVEL_HIGH | Active | Memory enable signal for port A. Must be high on clock cycles when read operations are initiated. Pipelined internally. |
| injectdbiterra | Input | 1 | clka | LEVEL_HIGH | 0 | Do not change from the provided value. |
| injectsbiterra | Input | 1 | clka | LEVEL_HIGH | 0 | Do not change from the provided value. |
| regcea | Input | 1 | clka | LEVEL_HIGH | 1 | Do not change from the provided value. |
| rsta | Input | 1 | clka | LEVEL_HIGH | Active | Reset signal for the final port A output register stage. Synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A. |
| sbiterra | Output | 1 | clka | LEVEL_HIGH | DoNotCare | Leave open. |
| sleep | Input | 1 | NA | LEVEL_HIGH | 0 | sleep signal to enable the dynamic power saving feature. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| ADDR_WIDTH_A | DECIMAL | 1 to 20 | 6 | Specify the width of the port A address port addra, in bits. Must be large enough to access the entire memory from port A, i.e. >= $clog2(MEMORY_SIZE/READ_DATA_WIDTH_A). |
| AUTO_SLEEP_TIME | DECIMAL | 0 to 15 | 0 | Must be set to 0 0 - Disable auto-sleep feature |
| CASCADE_HEIGHT | DECIMAL | 0 to 64 | 0 |
0- No Cascade Height, Allow Vivado Synthesis to choose. 1 or more - Vivado Synthesis sets the specified value as Cascade Height. |
| ECC_MODE | STRING | "no_ecc", "both_encode_and_decode", "decode_only", "encode_only" | "no_ecc" |
|
| MEMORY_INIT_FILE | STRING | String | "none" | Specify "none" (including quotes) for no memory initialization, or specify the name of a memory initialization file- Enter only the name of the file with .mem extension, including quotes but without path (e.g. "my_file.mem"). File format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. Initialization of memory happens through the file name specified only when parameter MEMORY_INIT_PARAM value is equal to "". When using XPM_MEMORY in a project, add the specified file to the Vivado project as a design source. |
| MEMORY_INIT_PARAM | STRING | String | "0" |
Specify "" or "0" (including quotes) for no memory initialization through parameter, or specify the string containing the hex characters. Enter only hex characters with each location separated by delimiter (,). Parameter format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. For example, if the narrowest data width is 8, and the depth of memory is 8 locations, then the parameter value should be passed as shown below. parameter MEMORY_INIT_PARAM = "AB,CD,EF,1,2,34,56,78" Where "AB" is the 0th location and "78" is the 7th location. |
| MEMORY_OPTIMIZATION | STRING | "true", "false" | "true" | Specify "true" to enable the optimization of unused memory or bits in the memory structure. Specify "false" to disable the optimization of unused memory or bits in the memory structure |
| MEMORY_PRIMITIVE | STRING | "auto", "block", "distributed", "ultra" | "auto" | Designate the memory primitive (resource type) to use- "auto"- Allow Vivado Synthesis to choose "distributed"- Distributed memory "block"- Block memory |
| MEMORY_SIZE | DECIMAL | 2 to 150994944 | 2048 | Specify the total memory array size, in bits. For example, enter 65536 for a 2kx32 ROM. |
| MESSAGE_CONTROL | DECIMAL | 0 to 1 | 0 | Specify 1 to enable the dynamic message reporting such as collision warnings, and 0 to disable the message reporting |
| READ_DATA_WIDTH_A | DECIMAL | 1 to 4608 | 32 | Specify the width of the port A read data output port douta, in bits. |
| READ_LATENCY_A | DECIMAL | 0 to 100 | 2 | Specify the number of register stages in the port A read data pipeline. Read data output to port douta takes this number of clka cycles. To target block memory, a value of 1 or larger is required- 1 causes use of memory latch only; 2 causes use of output register. To target distributed memory, a value of 0 or larger is required- 0 indicates combinatorial output. Values larger than 2 synthesize additional flip-flops that are not retimed into memory primitives. |
| READ_RESET_VALUE_A | STRING | String | "0" | Specify the reset value of the port A final output register stage in response to rsta input port is assertion. For example, to reset the value of port douta to all 0s when READ_DATA_WIDTH_A is 32, specify 32HHHHh0. |
| RST_MODE_A | STRING | "SYNC", "ASYNC" | "SYNC" |
Describes the behaviour of the reset
|
| SIM_ASSERT_CHK | DECIMAL | 0 to 1 | 0 |
0- Disable simulation message reporting. Messages related to potential misuse will not be reported. 1- Enable simulation message reporting. Messages related to potential misuse will be reported. |
| USE_MEM_INIT | DECIMAL | 0 to 1 | 1 |
Specify 1 to enable the generation of below message and 0 to disable generation of the following message completely. "INFO - MEMORY_INIT_FILE and MEMORY_INIT_PARAM together specifies no memory initialization. Initial memory contents will be all 0s." NOTE: This message gets generated only when there is no Memory Initialization specified either through file or Parameter. |
| USE_MEM_INIT_MMI | DECIMAL | 0 to 1 | 0 |
Specify 1 to expose this memory information to be written out in the MMI file. |
| WAKEUP_TIME | STRING | "disable_sleep", "use_sleep_pin" | "disable_sleep" | Specify "disable_sleep" to disable dynamic power saving option, and specify "use_sleep_pin" to enable the dynamic power saving option |
VHDL Instantiation Template
Unless they already exist, copy the
following two statements and paste them before the entity declaration.
Library xpm;
use xpm.vcomponents.all;
-- xpm_memory_sprom: Single Port ROM
-- Xilinx Parameterized Macro, version 2022.2
xpm_memory_sprom_inst : xpm_memory_sprom
generic map (
ADDR_WIDTH_A => 6, -- DECIMAL
AUTO_SLEEP_TIME => 0, -- DECIMAL
CASCADE_HEIGHT => 0, -- DECIMAL
ECC_MODE => "no_ecc", -- String
MEMORY_INIT_FILE => "none", -- String
MEMORY_INIT_PARAM => "0", -- String
MEMORY_OPTIMIZATION => "true", -- String
MEMORY_PRIMITIVE => "auto", -- String
MEMORY_SIZE => 2048, -- DECIMAL
MESSAGE_CONTROL => 0, -- DECIMAL
READ_DATA_WIDTH_A => 32, -- DECIMAL
READ_LATENCY_A => 2, -- DECIMAL
READ_RESET_VALUE_A => "0", -- String
RST_MODE_A => "SYNC", -- String
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
USE_MEM_INIT => 1, -- DECIMAL
USE_MEM_INIT_MMI => 0, -- DECIMAL
WAKEUP_TIME => "disable_sleep" -- String
)
port map (
dbiterra => dbiterra, -- 1-bit output: Leave open.
douta => douta, -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
sbiterra => sbiterra, -- 1-bit output: Leave open.
addra => addra, -- ADDR_WIDTH_A-bit input: Address for port A read operations.
clka => clka, -- 1-bit input: Clock signal for port A.
ena => ena, -- 1-bit input: Memory enable signal for port A. Must be high on clock
-- cycles when read operations are initiated. Pipelined internally.
injectdbiterra => injectdbiterra, -- 1-bit input: Do not change from the provided value.
injectsbiterra => injectsbiterra, -- 1-bit input: Do not change from the provided value.
regcea => regcea, -- 1-bit input: Do not change from the provided value.
rsta => rsta, -- 1-bit input: Reset signal for the final port A output register
-- stage. Synchronously resets output port douta to the value specified
-- by parameter READ_RESET_VALUE_A.
sleep => sleep -- 1-bit input: sleep signal to enable the dynamic power saving feature.
);
-- End of xpm_memory_sprom_inst instantiation
Verilog Instantiation Template
// xpm_memory_sprom: Single Port ROM
// Xilinx Parameterized Macro, version 2022.2
xpm_memory_sprom #(
.ADDR_WIDTH_A(6), // DECIMAL
.AUTO_SLEEP_TIME(0), // DECIMAL
.CASCADE_HEIGHT(0), // DECIMAL
.ECC_MODE("no_ecc"), // String
.MEMORY_INIT_FILE("none"), // String
.MEMORY_INIT_PARAM("0"), // String
.MEMORY_OPTIMIZATION("true"), // String
.MEMORY_PRIMITIVE("auto"), // String
.MEMORY_SIZE(2048), // DECIMAL
.MESSAGE_CONTROL(0), // DECIMAL
.READ_DATA_WIDTH_A(32), // DECIMAL
.READ_LATENCY_A(2), // DECIMAL
.READ_RESET_VALUE_A("0"), // String
.RST_MODE_A("SYNC"), // String
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.USE_MEM_INIT(1), // DECIMAL
.USE_MEM_INIT_MMI(0), // DECIMAL
.WAKEUP_TIME("disable_sleep") // String
)
xpm_memory_sprom_inst (
.dbiterra(dbiterra), // 1-bit output: Leave open.
.douta(douta), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
.sbiterra(sbiterra), // 1-bit output: Leave open.
.addra(addra), // ADDR_WIDTH_A-bit input: Address for port A read operations.
.clka(clka), // 1-bit input: Clock signal for port A.
.ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on clock
// cycles when read operations are initiated. Pipelined internally.
.injectdbiterra(injectdbiterra), // 1-bit input: Do not change from the provided value.
.injectsbiterra(injectsbiterra), // 1-bit input: Do not change from the provided value.
.regcea(regcea), // 1-bit input: Do not change from the provided value.
.rsta(rsta), // 1-bit input: Reset signal for the final port A output register stage.
// Synchronously resets output port douta to the value specified by
// parameter READ_RESET_VALUE_A.
.sleep(sleep) // 1-bit input: sleep signal to enable the dynamic power saving feature.
);
// End of xpm_memory_sprom_inst instantiation