Parameterized Macro: Synchronous Reset Synchronizer
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro synchronizes a reset singal to the destination clock domain. Unlike the XPM_CDC_ASYNC_RST macro, the generated output will both assert and deassert synchronously to the destination clock domain.
For proper operation, the input data must be sampled two or more times by the destination clock. You can define the number of register stages used in the synchronizers and the initial value of these registers after configuration. You can also enable a simulation feature to generate messages which report any potential misuse of the macro.
Port Descriptions
Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_clk | Input | 1 | NA | EDGE_RISING | Active | Destination clock. |
dest_rst | Output | 1 | dest_clk | NA | Active | src_rst synchronized to the destination clock domain. This output is registered. |
src_rst | Input | 1 | NA | NA | Active | Source reset signal. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the destination clock domain. |
INIT | DECIMAL | 1, 0 | 1 |
0- Initializes synchronization registers to 0 1- Initializes synchronization registers to 1 The option to initialize the synchronization registers means that there is no complete x-propagation behavior modeled in this macro. For complete x-propagation modelling, use the xpm_cdc_single macro. |
INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
0- Disable behavioral simulation initialization value(s) on synchronization registers. 1- Enable behavioral simulation initialization value(s) on synchronization registers. |
SIM_ASSERT_CHK | DECIMAL | 0, 1 | 0 |
0- Disable simulation message reporting. Messages related to potential misuse will not be reported. 1- Enable simulation message reporting. Messages related to potential misuse will be reported. |
VHDL Instantiation Template
Library xpm;
use xpm.vcomponents.all;
-- xpm_cdc_sync_rst: Synchronous Reset Synchronizer
-- Xilinx Parameterized Macro, version 2022.2
xpm_cdc_sync_rst_inst : xpm_cdc_sync_rst
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT => 1, -- DECIMAL; 0=initialize synchronization registers to 0, 1=initialize
-- synchronization registers to 1
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0 -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
)
port map (
dest_rst => dest_rst, -- 1-bit output: src_rst synchronized to the destination clock domain. This output
-- is registered.
dest_clk => dest_clk, -- 1-bit input: Destination clock.
src_rst => src_rst -- 1-bit input: Source reset signal.
);
-- End of xpm_cdc_sync_rst_inst instantiation
Verilog Instantiation Template
// xpm_cdc_sync_rst: Synchronous Reset Synchronizer
// Xilinx Parameterized Macro, version 2022.2
xpm_cdc_sync_rst #(
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
.INIT(1), // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization
// registers to 1
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK(0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
)
xpm_cdc_sync_rst_inst (
.dest_rst(dest_rst), // 1-bit output: src_rst synchronized to the destination clock domain. This output
// is registered.
.dest_clk(dest_clk), // 1-bit input: Destination clock.
.src_rst(src_rst) // 1-bit input: Source reset signal.
);
// End of xpm_cdc_sync_rst_inst instantiation