Primitive: VREF Scan
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
Introduction
The XPIO_VREF component, used with the IBUFE3, IOBUFE3, or IOBUFDSE3 buffers, provides access to the VREF scan capability in the XPIO banks.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| FABRIC_VREF_TUNE<9:0> | Input | 10 | VREF tuning input value to allow Vref adjustment. |
| VREF | Output | 1 | Tuned output that connects to all associated IBUFE3, IOBUFE3, or IOBUFDSE3 components within an XPIO bank. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | Recommended |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| ISTANDARD | STRING | String | "UNUSED" | |
| VOH | DECIMAL | 0 to 100 | 100 | |
| VREF_NIB | STRING | "VREF_MC", "VREF _FABRIC", "VREF_RIU" | "VREF _MC" |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- XPIO_VREF: VREF Scan
-- Versal Premium series
-- Xilinx HDL Language Template, version 2022.2
XPIO_VREF_inst : XPIO_VREF
port map (
VREF => VREF, -- 1-bit output: Tuned output (connect to associated IBUFE3
-- component)
FABRIC_VREF_TUNE => FABRIC_VREF_TUNE -- 10-bit input: VREF tuning value
);
-- End of XPIO_VREF_inst instantiation
Verilog Instantiation Template
// XPIO_VREF: VREF Scan
// Versal Premium series
// Xilinx HDL Language Template, version 2022.2
XPIO_VREF XPIO_VREF_inst (
.VREF(VREF), // 1-bit output: Tuned output (connect to associated IBUFE3
// component)
.FABRIC_VREF_TUNE(FABRIC_VREF_TUNE) // 10-bit input: VREF tuning value
);
// End of XPIO_VREF_inst instantiation
Related Information
- Versal ACAP SelectIO Resources Architecture Manual (AM010)