Primitive: Gigabit Transceiver Buffer
- PRIMITIVE_GROUP: ADVANCED
- PRIMITIVE_SUBGROUP: GT
Introduction
OBUFDS_GTE5_ADV is the gigabit transceiver output pad buffer component in Versal devices. The REFCLK signal should be routed to the dedicated reference clock output pins on the serial transceiver, and the user design should instantiate the OBUFDS_GTE5_ADV primitive in the user design. See the Transceivers User Guide for more information on PCB layout requirements, including reference clock requirements.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| CEB | Input | 1 | Reference the Versal ACAP Transceivers Architecture Manual for more information |
| I<3:0> | Input | 4 | Reference the Versal ACAP Transceivers Architecture Manual for more information |
| O | Output | 1 | Reference the Versal ACAP Transceivers Architecture Manual for more information |
| OB | Output | 1 | Reference the Versal ACAP Transceivers Architecture Manual for more information |
| RXRECCLKSEL<1:0> | Input | 2 | Reference the Versal ACAP Transceivers Architecture Manual for more information |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | Recommended |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| REFCLK_EN_DRV | BINARY | 1'b0 to 1'b1 | 1'b1 | Reference the Versal ACAP Transceivers Architecture Manual for more information |
| REFCLK_EN_TX_PATH | BINARY | 1'b0 to 1'b1 | 1'b1 | Reference the Versal ACAP Transceivers Architecture Manual for more information |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFDS_GTE5_ADV: Gigabit Transceiver Buffer
-- Versal Premium series
-- Xilinx HDL Language Template, version 2022.2
OBUFDS_GTE5_ADV_inst : OBUFDS_GTE5_ADV
generic map (
REFCLK_EN_DRV => '1', -- Reference the Versal ACAP Transceivers Architecture Manual for more
-- information
REFCLK_EN_TX_PATH => '1' -- Reference the Versal ACAP Transceivers Architecture Manual for more
-- information
)
port map (
O => O, -- 1-bit output: Reference the Versal ACAP Transceivers Architecture Manual
-- for more information
OB => OB, -- 1-bit output: Reference the Versal ACAP Transceivers Architecture Manual
-- for more information
CEB => CEB, -- 1-bit input: Reference the Versal ACAP Transceivers Architecture Manual
-- for more information
I => I, -- 4-bit input: Reference the Versal ACAP Transceivers Architecture Manual
-- for more information
RXRECCLKSEL => RXRECCLKSEL -- 2-bit input: Reference the Versal ACAP Transceivers Architecture Manual
-- for more information
);
-- End of OBUFDS_GTE5_ADV_inst instantiation
Verilog Instantiation Template
// OBUFDS_GTE5_ADV: Gigabit Transceiver Buffer
// Versal Premium series
// Xilinx HDL Language Template, version 2022.2
OBUFDS_GTE5_ADV #(
.REFCLK_EN_DRV(1'b1), // Reference the Versal ACAP Transceivers Architecture Manual for more
// information
.REFCLK_EN_TX_PATH(1'b1) // Reference the Versal ACAP Transceivers Architecture Manual for more
// information
)
OBUFDS_GTE5_ADV_inst (
.O(O), // 1-bit output: Reference the Versal ACAP Transceivers Architecture Manual
// for more information
.OB(OB), // 1-bit output: Reference the Versal ACAP Transceivers Architecture Manual
// for more information
.CEB(CEB), // 1-bit input: Reference the Versal ACAP Transceivers Architecture Manual for
// more information
.I(I), // 4-bit input: Reference the Versal ACAP Transceivers Architecture Manual for
// more information
.RXRECCLKSEL(RXRECCLKSEL) // 2-bit input: Reference the Versal ACAP Transceivers Architecture Manual for
// more information
);
// End of OBUFDS_GTE5_ADV_inst instantiation
Related Information
- Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002)