MMCME5 - 2022.2 English

Versal Architecture Premium Series Libraries Guide (UG1485)
Document ID
UG1485
Release Date
2022-10-19
Version
2022.2 English

Primitive: Mixed Mode Clock Manager (MMCM)

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: PLL

Introduction

The MMCME5 is a mixed signal block design to support frequency synthesis, clock network deskew, and jitter reduction. The clock outputs can each have an individual divide, phase shift, and duty cycle based on the same VCO frequency. Additionally, the MMCME5 supports dynamic phase shifting and fractional divides.

Port Descriptions

Port Direction Width Function
CLKFBIN Input 1 Feedback clock pin to the MMCM.
CLKFBOUT Output 1 Dedicated MMCM Feedback clock output.
CLKFBSTOPPED Output 1 Status pin indicating that the feedback clock has stopped.
CLKFB1_DESKEW Input 1 Secondary (feedback) clock input to the PD1 block for deskewing clock network delays.
CLKFB2_DESKEW Input 1 Secondary (feedback) clock input to the PD2 block for deskewing clock network delays.
CLKINSEL Input 1 Signal controls the state of the input MUX, High = CLKIN1, Low = CLKIN2.
CLKINSTOPPED Output 1 Status pin indicating that the input clock has stopped.
CLKIN1 Input 1 Primary clock input
CLKIN1_DESKEW Input 1 Primary clock input to the PD1 block for deskewing clock network delays between two different CLKOUT networks.
CLKIN2 Input 1 Secondary clock input to dynamically switch the MMCM reference clock.
CLKIN2_DESKEW Input 1 Primary clock input to the PD2 block for deskewing clock network delays between two different CLKOUT networks.
CLKOUT0 Output 1 CLKOUT0 output.
CLKOUT1 Output 1 CLKOUT1 output.
CLKOUT2 Output 1 CLKOUT2 output.
CLKOUT3 Output 1 CLKOUT3 output.
CLKOUT4 Output 1 CLKOUT4 output.
CLKOUT5 Output 1 CLKOUT5 output.
CLKOUT6 Output 1 CLKOUT6 output.
DADDR<6:0> Input 7 The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
DCLK Input 1 The DCLK signal is the reference clock for the dynamic reconfiguration port.
DEN Input 1 The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DI<15:0> Input 16 The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero.
DO<15:0> Output 16 The dynamic reconfiguration output bus provides MMCM data output when using dynamic reconfiguration
DRDY Output 1 The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the MMCMs dynamic reconfiguration feature.
DWE Input 1 The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low.
LOCKED Output 1 The LOCKED signal indicates that all functions requiring a LOCKED signal for the MMCM to operate properly have LOCKED. This LOCKED signal is therefore an AND function of LOCKED_FB, LOCKED1_DESKEW, and LOCKED2_DESKEW if used.
LOCKED_FB Output 1 An output from the MMCM that indicates when the MMCM has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The MMCM automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The MMCM must be reset after LOCKED is deasserted.
LOCKED1_DESKEW Output 1 Indicates if the PD1 circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits.
LOCKED2_DESKEW Output 1 Indicates if the PD2 circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits.
PSCLK Input 1 Phase shift clock.
PSDONE Output 1 Phase shift done.
PSEN Input 1 Phase shift enable.
PSINCDEC Input 1 Phase shift increment/decrement control.
PWRDWN Input 1 Powers down instantiated but unused MMCMs.
RST Input 1 Asynchronous reset signal. The RST signal is an asynchronous reset for the MMCM. The MMCM synchronously re-enables itself when this signal is released (that is, MMCM re-enabled). A reset is required when the input clock conditions change (for example, frequency).

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
BANDWIDTH STRING "OPTIMIZED", "HIGH", "LOW" "OPTIMIZED" Specified the MMCM programming algorithm affecting the jitter, phase margin, and other characteristics of the MMCM.
CLKFBOUT_FRACT DECIMAL 0 to 63 0 6-bit fractional M feedback divider in increments of 1/63. Generates a fraction of the CLKFBOUT_MULT value and adds it to CLKFBOUT_MULT.
CLKFBOUT_MULT DECIMAL 4 to 432 42 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency.
CLKFBOUT_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM.
CLKIN1_PERIOD FLOAT(nS) 0.000 to 100.000 0.000 Specifies the input period to the CLKIN1 in ns.
CLKIN2_PERIOD FLOAT(nS) 0.000 to 100.000 0.000 Specifies the input period to the CLKIN2 in ns.
CLKOUTFB_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKFBOUT counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface
Note: Other binary values are not valid.
CLKOUT0_DIVIDE DECIMAL 2 to 511 2 Specifies the amount to divide the CLKOUT0 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT0_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT0 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT0_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT0 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT0_DIVIDE) / 8
CLKOUT0_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT0 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface
Note: Other binary values are not valid.
CLKOUT1_DIVIDE DECIMAL 2 to 511 2 Specifies the amount to divide the CLKOUT1 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT1_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT1 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT1_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT1 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT1_DIVIDE) / 8
CLKOUT1_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT0 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface
Note: Other binary values are not valid.
CLKOUT2_DIVIDE DECIMAL 2 to 511 2 Specifies the amount to divide the CLKOUT2 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT2_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT2 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT2_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT2 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT2_DIVIDE) / 8
CLKOUT2_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT2 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface
Note: Other binary values are not valid.
CLKOUT3_DIVIDE DECIMAL 2 to 511 2 Specifies the amount to divide the CLKOUT3 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT3_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT3 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT3_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT3 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT3_DIVIDE) / 8
CLKOUT3_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT3 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface
Note: Other binary values are not valid.
CLKOUT4_DIVIDE DECIMAL 2 to 511 2 Specifies the amount to divide the CLKOUT4 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT4_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT4 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT4_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT4 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT4_DIVIDE) / 8
CLKOUT4_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT4 counter variable fine phase shift or deskew select
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface
Note: Other binary values are not valid.
CLKOUT5_DIVIDE DECIMAL 2 to 511 2 Specifies the amount to divide the CLKOUT5 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT5_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT5 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT5_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT5 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT5_DIVIDE) / 8
CLKOUT5_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT5 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface.
Note: Other binary values are not valid.
CLKOUT6_DIVIDE DECIMAL 2 to 511 2 Specifies the amount to divide the CLKOUT6 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT6_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT6 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT6_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT6 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT6_DIVIDE) / 8
CLKOUT6_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT6 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface.
Note: Other binary values are not valid.
COMPENSATION STRING "AUTO", "BUF_IN", "EXTERNAL", "INTERNAL" "AUTO" Clock input compensation. Should be set to AUTO. Defines how the MMCM feedback is configured.
  • "EXTERNAL": Indicates that a network external to the device is being compensated.
  • "INTERNAL": Indicates that the MMCM is using its own internal feedback path so no delay is being compensated.
  • "BUF_IN": Indicates that the clock network delay within the same XIPHY bank is compensated. The feedback must be limited to within the same XIPHY and cannot be routed to adjacent banks or outside the device.
  • "PHY_ALIGN": Allows fine-grain adjustments of the PLL output phase for the alignment of the XIPHY and internal logic flip-flops using the same source clock. Primarily for memory controller use.
DESKEW_DELAY_EN1 STRING "FALSE", "TRUE" "FALSE" Set to TRUE to enable the optional programmable delay in the PD1 circuit.
DESKEW_DELAY_EN2 STRING "FALSE", "TRUE" "FALSE" Set to TRUE to enable the optional programmable delay in the PD2 circuit.
DESKEW_DELAY_PATH1 STRING "FALSE", "TRUE" "FALSE" Determines if the CLKIN1_DESKEW path or the CLKFB1_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB1_DESKEW, FALSE = CLKIN1_DESKEW.
DESKEW_DELAY_PATH2 STRING "FALSE", "TRUE" "FALSE" Determines if the CLKIN2_DESKEW path or the CLKFB2_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB2_DESKEW, FALSE = CLKIN2_DESKEW.
DESKEW_DELAY1 DECIMAL 0 to 63 0 Value of the optional programmable delay in the PD1 circuit.
DESKEW_DELAY2 DECIMAL 0 to 63 0 Value of the optional programmable delay in the PD2 circuit.
DIVCLK_DIVIDE DECIMAL 1 to 123 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
IS_CLKFBIN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFBIN pin.
IS_CLKFB1_DESKEW_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFB1_DESKEW pin.
IS_CLKFB2_DESKEW_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFB2_DESKEW pin.
IS_CLKINSEL_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKINSEL pin.
IS_CLKIN1_DESKEW_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN1_DESKEW pin.
IS_CLKIN1_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN1 pin.
IS_CLKIN2_DESKEW_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN2_DESKEW pin.
IS_CLKIN2_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN2 pin.
IS_PSEN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PSEN pin.
IS_PSINCDEC_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PSINCDEC pin.
IS_PWRDWN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PWRDWN pin.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RST pin.
LOCK_WAIT STRING "FALSE", "TRUE" "FALSE" Wait during the configuration for the startup for the MMCM to lock.
REF_JITTER1 3 significant digit FLOAT 0.000 to 0.200 0.010 Specifies the expected jitter on the CLKIN1.
REF_JITTER2 3 significant digit FLOAT 0.000 to 0.200 0.010 Specifies the expected jitter on the CLKIN2.
SS_EN STRING "FALSE", "TRUE" "FALSE" Enables the spread spectrum feature for the MMCM. Used in conjunction with SS_MODE and SS_MOD_PERIOD attributes.
SS_MOD_PERIOD DECIMAL(nS) 4000 to 40000 10000 Specifies the spread spectrum modulation period (ns).
SS_MODE STRING "CENTER_HIGH", "CENTER_LOW", "DOWN_HIGH", "DOWN_LOW" "CENTER_HIGH" Controls the spread spectrum frequency deviation and the spread type.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- MMCME5: Mixed Mode Clock Manager (MMCM)
--         Versal Premium series
-- Xilinx HDL Language Template, version 2022.2

MMCME5_inst : MMCME5
generic map (
   BANDWIDTH => "OPTIMIZED",         -- HIGH, LOW, OPTIMIZED
   CLKFBOUT_FRACT => 0,              -- 6-bit fraction M feedback divider (0-63)
   CLKFBOUT_MULT => 42,              -- Multiply value for all CLKOUT, (4-432)
   CLKFBOUT_PHASE => 0.0,            -- Phase offset in degrees of CLKFB
   CLKIN1_PERIOD => 0.0,             -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   CLKIN2_PERIOD => 0.0,             -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   CLKOUT0_DIVIDE => 2,              -- Divide amount for CLKOUT0 (2-511)
   CLKOUT0_DUTY_CYCLE => 0.5,        -- Duty cycle for CLKOUT0
   CLKOUT0_PHASE => 0.0,             -- Phase offset for CLKOUT0
   CLKOUT0_PHASE_CTRL => "00",       -- CLKOUT0 fine phase shift or deskew select (0-11)
   CLKOUT1_DIVIDE => 2,              -- Divide amount for CLKOUT1 (2-511)
   CLKOUT1_DUTY_CYCLE => 0.5,        -- Duty cycle for CLKOUT1
   CLKOUT1_PHASE => 0.0,             -- Phase offset for CLKOUT1
   CLKOUT1_PHASE_CTRL => "00",       -- CLKOUT1 fine phase shift or deskew select (0-11)
   CLKOUT2_DIVIDE => 2,              -- Divide amount for CLKOUT2 (2-511)
   CLKOUT2_DUTY_CYCLE => 0.5,        -- Duty cycle for CLKOUT2
   CLKOUT2_PHASE => 0.0,             -- Phase offset for CLKOUT2
   CLKOUT2_PHASE_CTRL => "00",       -- CLKOUT2 fine phase shift or deskew select (0-11)
   CLKOUT3_DIVIDE => 2,              -- Divide amount for CLKOUT3 (2-511)
   CLKOUT3_DUTY_CYCLE => 0.5,        -- Duty cycle for CLKOUT3
   CLKOUT3_PHASE => 0.0,             -- Phase offset for CLKOUT3
   CLKOUT3_PHASE_CTRL => "00",       -- CLKOUT3 fine phase shift or deskew select (0-11)
   CLKOUT4_DIVIDE => 2,              -- Divide amount for CLKOUT4 (2-511)
   CLKOUT4_DUTY_CYCLE => 0.5,        -- Duty cycle for CLKOUT4
   CLKOUT4_PHASE => 0.0,             -- Phase offset for CLKOUT4
   CLKOUT4_PHASE_CTRL => "00",       -- CLKOUT4 fine phase shift or deskew select (0-11)
   CLKOUT5_DIVIDE => 2,              -- Divide amount for CLKOUT5 (2-511)
   CLKOUT5_DUTY_CYCLE => 0.5,        -- Duty cycle for CLKOUT5
   CLKOUT5_PHASE => 0.0,             -- Phase offset for CLKOUT5
   CLKOUT5_PHASE_CTRL => "00",       -- CLKOUT5 fine phase shift or deskew select (0-11)
   CLKOUT6_DIVIDE => 2,              -- Divide amount for CLKOUT6 (2-511)
   CLKOUT6_DUTY_CYCLE => 0.5,        -- Duty cycle for CLKOUT6
   CLKOUT6_PHASE => 0.0,             -- Phase offset for CLKOUT6
   CLKOUT6_PHASE_CTRL => "00",       -- CLKOUT6 fine phase shift or deskew select (0-11)
   CLKOUTFB_PHASE_CTRL => "00",      -- CLKFBOUT fine phase shift or deskew select (0-11)
   COMPENSATION => "AUTO",           -- Clock input compensation
   DESKEW_DELAY1 => 0,               -- Deskew optional programmable delay
   DESKEW_DELAY2 => 0,               -- Deskew optional programmable delay
   DESKEW_DELAY_EN1 => "FALSE",      -- Enable deskew optional programmable delay
   DESKEW_DELAY_EN2 => "FALSE",      -- Enable deskew optional programmable delay
   DESKEW_DELAY_PATH1 => "FALSE",    -- Select CLKIN1_DESKEW (TRUE) or CLKFB1_DESKEW (FALSE)
   DESKEW_DELAY_PATH2 => "FALSE",    -- Select CLKIN2_DESKEW (TRUE) or CLKFB2_DESKEW (FALSE)
   DIVCLK_DIVIDE => 1,               -- Master division value
   IS_CLKFB1_DESKEW_INVERTED => '0', -- Optional inversion for CLKFB1_DESKEW
   IS_CLKFB2_DESKEW_INVERTED => '0', -- Optional inversion for CLKFB2_DESKEW
   IS_CLKFBIN_INVERTED => '0',       -- Optional inversion for CLKFBIN
   IS_CLKIN1_DESKEW_INVERTED => '0', -- Optional inversion for CLKIN1_DESKEW
   IS_CLKIN1_INVERTED => '0',        -- Optional inversion for CLKIN1
   IS_CLKIN2_DESKEW_INVERTED => '0', -- Optional inversion for CLKIN2_DESKEW
   IS_CLKIN2_INVERTED => '0',        -- Optional inversion for CLKIN2
   IS_CLKINSEL_INVERTED => '0',      -- Optional inversion for CLKINSEL
   IS_PSEN_INVERTED => '0',          -- Optional inversion for PSEN
   IS_PSINCDEC_INVERTED => '0',      -- Optional inversion for PSINCDEC
   IS_PWRDWN_INVERTED => '0',        -- Optional inversion for PWRDWN
   IS_RST_INVERTED => '0',           -- Optional inversion for RST
   LOCK_WAIT => "FALSE",             -- Lock wait
   REF_JITTER1 => 0.0,               -- Reference input jitter in UI (0.000-0.200).
   REF_JITTER2 => 0.0,               -- Reference input jitter in UI (0.000-0.200).
   SS_EN => "FALSE",                 -- Enables spread spectrum
   SS_MODE => "CENTER_HIGH",         -- Spread spectrum frequency deviation and the spread type
   SS_MOD_PERIOD => 10000            -- Spread spectrum modulation period (ns)
)
port map (
   CLKFBOUT => CLKFBOUT,             -- 1-bit output: Feedback clock
   CLKFBSTOPPED => CLKFBSTOPPED,     -- 1-bit output: Feedback clock stopped
   CLKINSTOPPED => CLKINSTOPPED,     -- 1-bit output: Input clock stopped
   CLKOUT0 => CLKOUT0,               -- 1-bit output: CLKOUT0
   CLKOUT1 => CLKOUT1,               -- 1-bit output: CLKOUT1
   CLKOUT2 => CLKOUT2,               -- 1-bit output: CLKOUT2
   CLKOUT3 => CLKOUT3,               -- 1-bit output: CLKOUT3
   CLKOUT4 => CLKOUT4,               -- 1-bit output: CLKOUT4
   CLKOUT5 => CLKOUT5,               -- 1-bit output: CLKOUT5
   CLKOUT6 => CLKOUT6,               -- 1-bit output: CLKOUT6
   DO => DO,                         -- 16-bit output: DRP data output
   DRDY => DRDY,                     -- 1-bit output: DRP ready
   LOCKED => LOCKED,                 -- 1-bit output: LOCK
   LOCKED1_DESKEW => LOCKED1_DESKEW, -- 1-bit output: LOCK DESKEW PD1
   LOCKED2_DESKEW => LOCKED2_DESKEW, -- 1-bit output: LOCK DESKEW PD2
   LOCKED_FB => LOCKED_FB,           -- 1-bit output: LOCK FEEDBACK
   PSDONE => PSDONE,                 -- 1-bit output: Phase shift done
   CLKFB1_DESKEW => CLKFB1_DESKEW,   -- 1-bit input: Secondary clock input to PD1
   CLKFB2_DESKEW => CLKFB2_DESKEW,   -- 1-bit input: Secondary clock input to PD2
   CLKFBIN => CLKFBIN,               -- 1-bit input: Feedback clock
   CLKIN1 => CLKIN1,                 -- 1-bit input: Primary clock
   CLKIN1_DESKEW => CLKIN1_DESKEW,   -- 1-bit input: Primary clock input to PD1
   CLKIN2 => CLKIN2,                 -- 1-bit input: Secondary clock
   CLKIN2_DESKEW => CLKIN2_DESKEW,   -- 1-bit input: Primary clock input to PD2
   CLKINSEL => CLKINSEL,             -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
   DADDR => DADDR,                   -- 7-bit input: DRP address
   DCLK => DCLK,                     -- 1-bit input: DRP clock
   DEN => DEN,                       -- 1-bit input: DRP enable
   DI => DI,                         -- 16-bit input: DRP data input
   DWE => DWE,                       -- 1-bit input: DRP write enable
   PSCLK => PSCLK,                   -- 1-bit input: Phase shift clock
   PSEN => PSEN,                     -- 1-bit input: Phase shift enable
   PSINCDEC => PSINCDEC,             -- 1-bit input: Phase shift increment/decrement
   PWRDWN => PWRDWN,                 -- 1-bit input: Power-down
   RST => RST                        -- 1-bit input: Reset
);

-- End of MMCME5_inst instantiation

Verilog Instantiation Template


// MMCME5: Mixed Mode Clock Manager (MMCM)
//         Versal Premium series
// Xilinx HDL Language Template, version 2022.2

MMCME5 #(
   .BANDWIDTH("OPTIMIZED"),          // HIGH, LOW, OPTIMIZED
   .CLKFBOUT_FRACT(0),               // 6-bit fraction M feedback divider (0-63)
   .CLKFBOUT_MULT(42),               // Multiply value for all CLKOUT, (4-432)
   .CLKFBOUT_PHASE(0.0),             // Phase offset in degrees of CLKFB
   .CLKIN1_PERIOD(0.0),              // Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   .CLKIN2_PERIOD(0.0),              // Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   .CLKOUT0_DIVIDE(2),               // Divide amount for CLKOUT0 (2-511)
   .CLKOUT0_DUTY_CYCLE(0.5),         // Duty cycle for CLKOUT0
   .CLKOUT0_PHASE(0.0),              // Phase offset for CLKOUT0
   .CLKOUT0_PHASE_CTRL(2'b00),       // CLKOUT0 fine phase shift or deskew select (0-11)
   .CLKOUT1_DIVIDE(2),               // Divide amount for CLKOUT1 (2-511)
   .CLKOUT1_DUTY_CYCLE(0.5),         // Duty cycle for CLKOUT1
   .CLKOUT1_PHASE(0.0),              // Phase offset for CLKOUT1
   .CLKOUT1_PHASE_CTRL(2'b00),       // CLKOUT1 fine phase shift or deskew select (0-11)
   .CLKOUT2_DIVIDE(2),               // Divide amount for CLKOUT2 (2-511)
   .CLKOUT2_DUTY_CYCLE(0.5),         // Duty cycle for CLKOUT2
   .CLKOUT2_PHASE(0.0),              // Phase offset for CLKOUT2
   .CLKOUT2_PHASE_CTRL(2'b00),       // CLKOUT2 fine phase shift or deskew select (0-11)
   .CLKOUT3_DIVIDE(2),               // Divide amount for CLKOUT3 (2-511)
   .CLKOUT3_DUTY_CYCLE(0.5),         // Duty cycle for CLKOUT3
   .CLKOUT3_PHASE(0.0),              // Phase offset for CLKOUT3
   .CLKOUT3_PHASE_CTRL(2'b00),       // CLKOUT3 fine phase shift or deskew select (0-11)
   .CLKOUT4_DIVIDE(2),               // Divide amount for CLKOUT4 (2-511)
   .CLKOUT4_DUTY_CYCLE(0.5),         // Duty cycle for CLKOUT4
   .CLKOUT4_PHASE(0.0),              // Phase offset for CLKOUT4
   .CLKOUT4_PHASE_CTRL(2'b00),       // CLKOUT4 fine phase shift or deskew select (0-11)
   .CLKOUT5_DIVIDE(2),               // Divide amount for CLKOUT5 (2-511)
   .CLKOUT5_DUTY_CYCLE(0.5),         // Duty cycle for CLKOUT5
   .CLKOUT5_PHASE(0.0),              // Phase offset for CLKOUT5
   .CLKOUT5_PHASE_CTRL(2'b00),       // CLKOUT5 fine phase shift or deskew select (0-11)
   .CLKOUT6_DIVIDE(2),               // Divide amount for CLKOUT6 (2-511)
   .CLKOUT6_DUTY_CYCLE(0.5),         // Duty cycle for CLKOUT6
   .CLKOUT6_PHASE(0.0),              // Phase offset for CLKOUT6
   .CLKOUT6_PHASE_CTRL(2'b00),       // CLKOUT6 fine phase shift or deskew select (0-11)
   .CLKOUTFB_PHASE_CTRL(2'b00),      // CLKFBOUT fine phase shift or deskew select (0-11)
   .COMPENSATION("AUTO"),            // Clock input compensation
   .DESKEW_DELAY1(0),                // Deskew optional programmable delay
   .DESKEW_DELAY2(0),                // Deskew optional programmable delay
   .DESKEW_DELAY_EN1("FALSE"),       // Enable deskew optional programmable delay
   .DESKEW_DELAY_EN2("FALSE"),       // Enable deskew optional programmable delay
   .DESKEW_DELAY_PATH1("FALSE"),     // Select CLKIN1_DESKEW (TRUE) or CLKFB1_DESKEW (FALSE)
   .DESKEW_DELAY_PATH2("FALSE"),     // Select CLKIN2_DESKEW (TRUE) or CLKFB2_DESKEW (FALSE)
   .DIVCLK_DIVIDE(1),                // Master division value
   .IS_CLKFB1_DESKEW_INVERTED(1'b0), // Optional inversion for CLKFB1_DESKEW
   .IS_CLKFB2_DESKEW_INVERTED(1'b0), // Optional inversion for CLKFB2_DESKEW
   .IS_CLKFBIN_INVERTED(1'b0),       // Optional inversion for CLKFBIN
   .IS_CLKIN1_DESKEW_INVERTED(1'b0), // Optional inversion for CLKIN1_DESKEW
   .IS_CLKIN1_INVERTED(1'b0),        // Optional inversion for CLKIN1
   .IS_CLKIN2_DESKEW_INVERTED(1'b0), // Optional inversion for CLKIN2_DESKEW
   .IS_CLKIN2_INVERTED(1'b0),        // Optional inversion for CLKIN2
   .IS_CLKINSEL_INVERTED(1'b0),      // Optional inversion for CLKINSEL
   .IS_PSEN_INVERTED(1'b0),          // Optional inversion for PSEN
   .IS_PSINCDEC_INVERTED(1'b0),      // Optional inversion for PSINCDEC
   .IS_PWRDWN_INVERTED(1'b0),        // Optional inversion for PWRDWN
   .IS_RST_INVERTED(1'b0),           // Optional inversion for RST
   .LOCK_WAIT("FALSE"),              // Lock wait
   .REF_JITTER1(0.0),                // Reference input jitter in UI (0.000-0.200).
   .REF_JITTER2(0.0),                // Reference input jitter in UI (0.000-0.200).
   .SS_EN("FALSE"),                  // Enables spread spectrum
   .SS_MODE("CENTER_HIGH"),          // Spread spectrum frequency deviation and the spread type
   .SS_MOD_PERIOD(10000)             // Spread spectrum modulation period (ns)
)
MMCME5_inst (
   .CLKFBOUT(CLKFBOUT),             // 1-bit output: Feedback clock
   .CLKFBSTOPPED(CLKFBSTOPPED),     // 1-bit output: Feedback clock stopped
   .CLKINSTOPPED(CLKINSTOPPED),     // 1-bit output: Input clock stopped
   .CLKOUT0(CLKOUT0),               // 1-bit output: CLKOUT0
   .CLKOUT1(CLKOUT1),               // 1-bit output: CLKOUT1
   .CLKOUT2(CLKOUT2),               // 1-bit output: CLKOUT2
   .CLKOUT3(CLKOUT3),               // 1-bit output: CLKOUT3
   .CLKOUT4(CLKOUT4),               // 1-bit output: CLKOUT4
   .CLKOUT5(CLKOUT5),               // 1-bit output: CLKOUT5
   .CLKOUT6(CLKOUT6),               // 1-bit output: CLKOUT6
   .DO(DO),                         // 16-bit output: DRP data output
   .DRDY(DRDY),                     // 1-bit output: DRP ready
   .LOCKED(LOCKED),                 // 1-bit output: LOCK
   .LOCKED1_DESKEW(LOCKED1_DESKEW), // 1-bit output: LOCK DESKEW PD1
   .LOCKED2_DESKEW(LOCKED2_DESKEW), // 1-bit output: LOCK DESKEW PD2
   .LOCKED_FB(LOCKED_FB),           // 1-bit output: LOCK FEEDBACK
   .PSDONE(PSDONE),                 // 1-bit output: Phase shift done
   .CLKFB1_DESKEW(CLKFB1_DESKEW),   // 1-bit input: Secondary clock input to PD1
   .CLKFB2_DESKEW(CLKFB2_DESKEW),   // 1-bit input: Secondary clock input to PD2
   .CLKFBIN(CLKFBIN),               // 1-bit input: Feedback clock
   .CLKIN1(CLKIN1),                 // 1-bit input: Primary clock
   .CLKIN1_DESKEW(CLKIN1_DESKEW),   // 1-bit input: Primary clock input to PD1
   .CLKIN2(CLKIN2),                 // 1-bit input: Secondary clock
   .CLKIN2_DESKEW(CLKIN2_DESKEW),   // 1-bit input: Primary clock input to PD2
   .CLKINSEL(CLKINSEL),             // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
   .DADDR(DADDR),                   // 7-bit input: DRP address
   .DCLK(DCLK),                     // 1-bit input: DRP clock
   .DEN(DEN),                       // 1-bit input: DRP enable
   .DI(DI),                         // 16-bit input: DRP data input
   .DWE(DWE),                       // 1-bit input: DRP write enable
   .PSCLK(PSCLK),                   // 1-bit input: Phase shift clock
   .PSEN(PSEN),                     // 1-bit input: Phase shift enable
   .PSINCDEC(PSINCDEC),             // 1-bit input: Phase shift increment/decrement
   .PWRDWN(PWRDWN),                 // 1-bit input: Power-down
   .RST(RST)                        // 1-bit input: Reset
);

// End of MMCME5_inst instantiation

Related Information

  • Versal ACAP Clocking Resources Architecture Manual (AM003)