IOBUF - 2022.2 English

Primitive: Input/Output Buffer

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BIDIR_BUFFER

Introduction

The IOBUF primitive is needed when bidirectional signals require both an input buffer and a 3-state output buffer with an active-High 3-state T pin. The IOBUF is a generic IOBUF. A logic-High on the T pin disables the output buffer. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination (uncalibrated or DCI) are ON. When the output buffer is not 3-stated (T = Low), any on-die receiver termination (uncalibrated or DCI) is disabled.

I/O attributes that do not impact the logic function of the component such as IOSTANDARD, DRIVE and SLEW should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Logic Table

Inputs		Bidirectional	Outputs
T	I	IO	O
1	X	Z	IO
0	1	1	1
0	0	0	0

Port Descriptions

Port	Direction	Width	Function
I	Input	1	Input of OBUF. Connect to the logic driving the output port.
IO	Inout	1	Bidirectional port to be connected directly to top-level inout port.
O	Output	1	Output path of the buffer.
T	Input	1	3-state enable input signifying whether the buffer acts as an input or output.

Design Entry Method

Instantiation	Yes
Inference	Recommended
IP and IP Integrator Catalog	No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUF: Input/Output Buffer
--        Versal Premium series
-- Xilinx HDL Language Template, version 2022.2

IOBUF_inst : IOBUF
port map (
   O => O,   -- 1-bit output: Buffer output
   I => I,   -- 1-bit input: Buffer input
   IO => IO, -- 1-bit inout: Buffer inout (connect directly to top-level port)
   T => T    -- 1-bit input: 3-state enable input
);

-- End of IOBUF_inst instantiation

Verilog Instantiation Template


// IOBUF: Input/Output Buffer
//        Versal Premium series
// Xilinx HDL Language Template, version 2022.2

IOBUF IOBUF_inst (
   .O(O),   // 1-bit output: Buffer output
   .I(I),   // 1-bit input: Buffer input
   .IO(IO), // 1-bit inout: Buffer inout (connect directly to top-level port)
   .T(T)    // 1-bit input: 3-state enable input
);

// End of IOBUF_inst instantiation

Related Information

Versal ACAP SelectIO Resources Architecture Manual (AM010)