IBUFDS_DIFF_OUT - 2022.2 English

Primitive: Differential Input Buffer With Complementary Outputs

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: INPUT_BUFFER

Introduction

The IBUFDS_DIFF_OUT is a differential input buffer primitive with complementary outputs (O and OB).

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Logic Table

Inputs		Outputs
I	IB	O	OB
0	0	No Change	No Change
0	1	0	1
1	0	1	0
1	1	No Change	No Change

Port Descriptions

Port	Direction	Width	Function
I	Input	1	Diff_p Buffer Input. Connect to top-level p-side input port.
IB	Input	1	Diff_n Buffer Input. Connect to top-level n-side input port.
O	Output	1	Buffer diff_p output.
OB	Output	1	Buffer diff_n output.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IBUFDS_DIFF_OUT: Differential Input Buffer With Complementary Outputs
--                  Versal Premium series
-- Xilinx HDL Language Template, version 2022.2

IBUFDS_DIFF_OUT_inst : IBUFDS_DIFF_OUT
generic map (
   CCIO_EN_M => "TRUE",
   CCIO_EN_S => "TRUE"
)
port map (
   O => O,   -- 1-bit output: Buffer diff_p output
   OB => OB, -- 1-bit output: Buffer diff_n output
   I => I,   -- 1-bit input: Diff_p buffer input (connect directly to top-level port)
   IB => IB  -- 1-bit input: Diff_n buffer input (connect directly to top-level port)
);

-- End of IBUFDS_DIFF_OUT_inst instantiation

Verilog Instantiation Template


// IBUFDS_DIFF_OUT: Differential Input Buffer With Complementary Outputs
//                  Versal Premium series
// Xilinx HDL Language Template, version 2022.2

IBUFDS_DIFF_OUT #(
   .CCIO_EN_M("TRUE"),
   .CCIO_EN_S("TRUE")
)
IBUFDS_DIFF_OUT_inst (
   .O(O),   // 1-bit output: Buffer diff_p output
   .OB(OB), // 1-bit output: Buffer diff_n output
   .I(I),   // 1-bit input: Diff_p buffer input (connect directly to top-level port)
   .IB(IB)  // 1-bit input: Diff_n buffer input (connect directly to top-level port)
);

// End of IBUFDS_DIFF_OUT_inst instantiation

Related Information

Versal ACAP SelectIO Resources Architecture Manual (AM010)