BUFG_GT - 2022.2 English

Primitive: Clock Buffer Driven by Gigabit Transceiver

PRIMITIVE_GROUP: CLOCK
PRIMITIVE_SUBGROUP: BUFFER

Introduction

Clock buffer driven by the gigabit transceiver for the purpose of clock distribution to other portions of the device.

Port Descriptions

Port	Direction	Width	Function
CE	Input	1	Buffer enable.
CEMASK	Input	1	CE Mask.
CLR	Input	1	Asynchronous clear forcing the output to zero.
CLRMASK	Input	1	CLR Mask.
DIV<2:0>	Input	3	Specifies the value to divide the clock. Divide value is value provided plus 1. For instance, setting 3'b000 will provide a divide value of 1 and 3'b111 will be a divide value of 8.
I	Input	1	Buffer input.
O	Output	1	Buffer output.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Recommended

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- BUFG_GT: Clock Buffer Driven by Gigabit Transceiver
--          Versal Premium series
-- Xilinx HDL Language Template, version 2022.2

BUFG_GT_inst : BUFG_GT
generic map (
   SIM_DEVICE => "VERSAL_PREMIUM"  -- VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2
)
port map (
   O => O,             -- 1-bit output: Buffer
   CE => CE,           -- 1-bit input: Buffer enable
   CEMASK => CEMASK,   -- 1-bit input: CE Mask
   CLR => CLR,         -- 1-bit input: Asynchronous clear
   CLRMASK => CLRMASK, -- 1-bit input: CLR Mask
   DIV => DIV,         -- 3-bit input: Dynamic divide Value
   I => I              -- 1-bit input: Buffer
);

-- End of BUFG_GT_inst instantiation

Verilog Instantiation Template


// BUFG_GT: Clock Buffer Driven by Gigabit Transceiver
//          Versal Premium series
// Xilinx HDL Language Template, version 2022.2

BUFG_GT #(
   .SIM_DEVICE("VERSAL_PREMIUM")  // VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2
)
BUFG_GT_inst (
   .O(O),             // 1-bit output: Buffer
   .CE(CE),           // 1-bit input: Buffer enable
   .CEMASK(CEMASK),   // 1-bit input: CE Mask
   .CLR(CLR),         // 1-bit input: Asynchronous clear
   .CLRMASK(CLRMASK), // 1-bit input: CLR Mask
   .DIV(DIV),         // 3-bit input: Dynamic divide Value
   .I(I)              // 1-bit input: Buffer
);

// End of BUFG_GT_inst instantiation

Related Information

Versal ACAP Clocking Resources Architecture Manual (AM003)