AND2B1L - 2022.2 English

Versal Architecture Premium Series Libraries Guide (UG1485)

Document ID
UG1485
Release Date
2022-10-19
Version
2022.2 English

Primitive: Two input AND gate implemented in place of a CLB Latch

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LATCH

Introduction

This element allows the specification of a configurable CLB latch to take the function of a two input AND gate. This element can reduce logic levels and increase logic density of the part by trading off register/latch resources for logic. Xilinx suggests caution when using this component as it can affect register packing and density within a CLB.

Logic Table

Inputs Outputs
DI SRI O
0 0 0
0 1 0
1 0 1
1 1 0

Port Descriptions

Port Direction Width Function
DI Input 1 Active-High input that is generally connected to sourcing LUT located in the same CLB.
O Output 1 Output of the AND gate.
SRI Input 1 Input that is generally sourced from outside of the CLB. The attribute IS_SRI_INVERTED determines the active polarity of this signal.
Note: To allow more than one AND2B1L or OR2L to be packed into a half CLB, a common signal must be connected to this input.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
IS_SRI_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion for the SRI pin of this component. When set to High, the AND2B1L acts as a true AND gate.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- AND2B1L: Two input AND gate implemented in place of a CLB Latch
--          Versal Premium series
-- Xilinx HDL Language Template, version 2022.2

AND2B1L_inst : AND2B1L
generic map (
   IS_SRI_INVERTED => '0'  -- Optional inversion for SRI
)
port map (
   O => O,     -- 1-bit output: AND gate output
   DI => DI,   -- 1-bit input: Data input connected to LUT logic
   SRI => SRI  -- 1-bit input: External CLB data
);

-- End of AND2B1L_inst instantiation

Verilog Instantiation Template


// AND2B1L: Two input AND gate implemented in place of a CLB Latch
//          Versal Premium series
// Xilinx HDL Language Template, version 2022.2

AND2B1L #(
   .IS_SRI_INVERTED(1'b0)  // Optional inversion for SRI
)
AND2B1L_inst (
   .O(O),     // 1-bit output: AND gate output
   .DI(DI),   // 1-bit input: Data input connected to LUT logic
   .SRI(SRI)  // 1-bit input: External CLB data
);

// End of AND2B1L_inst instantiation

Related Information

  • Versal ACAP Configurable Logic Block Architecture Manual (AM005)