Vitis Model Composer Hub Block Parameters - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
Release Date
2022.2 English

Vitis Model Composer Hub Block Parameters

Tab Field in the Model Composer Hub Block Parameter Name Allowed Values
Hardware Selection Select Hardware SelectHardware Part or board name or platform file
Code Generation To select the subsystem in the left side panel SelectSubsystem 0 or 1
Code Generation (DUT) Code Directory CodeDirectory Directory
Code Generation (Hardware Flow) Generate Hardware Image GenerateHwImage 0 or 1
HW System Type HwSystemType BareMetal or Linux
Target HwTarget hw or hw_emu
Common SW Dir HWCommonSWDir Directory
Target SDK Dir TargetSDKDir Directory
Code Generation (HDL Subsystem) Compilation Type CompilationType  
Hardware Description HardwareDescription  
Synthesis Strategy SynthesisStrategy  
Implementation Strategy ImplementationStrategy  
Create Testbench CreateTestbench  
Enable Multiple clocks EnableMultipleClocks  
FPGA Clock Period FPGAClockPeriod  
Simulink System Period SimulinkSystemPeriod  
Clock pin location ClockPinLocation  
Provide Clock enable clear pin ProvideClockEnableClearPin  
Block Icon Display BlockIconDisplay  
Perform Analysis PerformAnalysis  
Analysis Type AnalyzerType  
Remote IP Cache RemoteIPCache  
Create Interface document CreateInterfaceDocument  
Code Generation (HLS Subsystem) Target Target  
FPGA Clock Frequency FPGAClockFrequency  
Throughput factor ThroughputFactor  
Create Testbench and run C simulation CreateTestbench  
Testbench stack size TestbenchStackSize  
Code Generation (AIE Subsystem) AIE Compiler Options AIECompilerOptions  
Create Testbench CreateTestbench  
Run cycle-approximate AIE simulation RunAIESimulation  
Simulation Timeout SimulationTimeout  
Plot AIE simulation output and Estimate throughput PlotAIESimulation  
Collect Profiling Statistics CollectProfilingStats  
Collect Data for Vitis Analyzer CollectDataForVitisAnalyzer