Verifying the C++ Code - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

When generating the output using the Vitis Model Composer Hub block, you also have the ability to Create and run C simulation. When selecting this option, you are enabling the Model Composer verification flow. This causes Model Composer to generate a few more output files, including a makefile, the test bench, tb.cpp, and signals.stim as previously discussed. The purpose of the test bench is to apply input stimuli, generated during Simulink simulation, to the top-level function of the generated C++ or RTL code and compare that function's output against the output samples captured in the signals.stim file. Depending on the output generated, the verification flow runs simulation on the C++ or RTL outputs generated by Model Composer and looks for the same result as generated by Simulink.

When the Target on the Model Composer Hub block is HLS C++ code, the verification flow is as follows:

  • The model is simulated in Simulink and the input and outputs are logged into the signals.stim binary file.
  • Model Composer generates the C++ code and a test bench, tb.cpp, which contains a main() function.
  • Model Composer launches simulation.
  • It verifies that the output from the generated C++ code matches the output logged from the Simulink simulation, signals.stim.
  • In case of a mismatch, the mismatched output signal name is reported, as well as the actual and expected values.
  • The result is a Pass/Fail returned by Model Composer.
Important: During simulation by Model Composer, you might receive the following error message:
Failed to find a XilinxLibrary block connected to input port.
This error simply means that there is an input in the subsystem that does not connect to a block from the HLS Library block set. This might be due to the presence of signals that you are simply passing through the subsystem for signal grouping, or improved readability. The recommended fix for this conditions is to connect the input to a Gain block from the Xilinx Toolbox > HLS > Math Functions > Math Operations block library, with the default value of 1, and Output data type same as input checked, as shown in the following figure.
Figure 1. Adding Gain to Unconnected Inputs