Vector Real Gateway In - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

The Vector Real Gateway In block converts vector inputs of type Simulink® integer, single, double, and fixed-point to Xilinx® fixed-point or floating-point data type.

Hardware notes: In hardware, these blocks become top level input ports.

Description

The Vector Real Gateway In blocks are the inputs into the HDL portion of your Simulink design. These blocks convert Simulink integer, double and fixed-point data types into the Model Composer fixed-point type. Each block defines a top-level input port or interface in the HDL design generated by Model Composer.

Conversion of Simulink Data to Model Composer Data

A number of different Simulink data types are supported on the input of Vector Real Gateway In. The data types supported include int8, uint8, int16, uint16, in32, uint32, single, double, and Simulink fixed-point data type(if Simulink fixed-point data type license is available). In all causes the input data is converted to a double internal to gateway, and then converted to target data type as specified on the Vector Real Gateway In block (Fixed-point, Floating-point or Boolean). When converting to Fixed-point from the internal double representation, the Quantization, and Overflow is further handled as specified in the Block GUI. For overflow, the options are to saturate to the largest positive/smallest negative value, to wrap (for example, to discard bits to the left of the most significant representable bit), or to flag an overflow as a Simulink error during simulation. For quantization, the options are to round to the nearest representable value (or to the value furthest from zero if there are two equidistant nearest representable values), or to truncate (for example, to discard bits to the right of the least significant representable bit). It is important to realize that conversion, overflow and quantization do not take place in hardware. They take place only in the simulation model of the block.

Gateway Blocks

As listed below, the Xilinx Vector Real Gateway In block is used to provide a number of functions:

  • Converting data from Simulink integer, double, and fixed-point type to the Model Composer fixed-point type during simulation in Simulink.
  • Defining top-level input ports or interface in the HDL design generated by Model Composer.
  • Defining test bench stimuli when the Create Testbench box is checked in the Model Composer Hub block. In this case, during HDL code generation, the inputs to the block that occur during Simulink simulation are logged as a logic vector in a data file. During HDL simulation, an entity that is inserted in the top level test bench checks this vector, and the corresponding vectors produced by Vector Real Gateway Out blocks against expected results.
  • Naming the corresponding port in the top level HDL entity.

Block Parameters

Open the Block Parameters dialog box by double-clicking the icon in your Simulink model.

Basic Tab

Parameters specific to the Basic tab are as follows:

Output Type
Specifies the output data type. Can be Boolean, Fixed-point, or Floating-point.
Super Sample Rate (SSR)
This configurable GUI parameter is primarily used to control processing of multiple data samples on every sample period. This block enables 1-D vector support for the primary block operation.
Arithmetic Type

If the Output Type is specified as Fixed-point, you can select Signed (2’s comp) or Unsigned as the Arithmetic Type.

Fixed-point Precision
Number of bits
Specifies the bit location of the binary point, where bit zero is the least significant bit.
Binary point
Specifies the bit location of the binary point, where bit zero is the least significant bit.
Floating-point Precision
Single
Specifies single precision (32 bits).
Double
Specifies double precision (64 bits).
Custom
Activates the field below so you can specify the Exponent width and the Fraction width.
Exponent width
Specify the exponent width.
Fraction width
Specify the fraction width.
Quantization

Quantization errors occur when the number of fractional bits is insufficient to represent the fractional portion of a value. The options are to Truncate (for example, to discard bits to the right of the least significant representable bit), Round(unbiased: +/- inf), or Round (unbiased: even values).

Round(unbiased: +/- inf) also known as "Symmetric Round (towards +/- inf)" or "Symmetric Round (away from zero)". This is similar to the MATLAB round() function. This method rounds the value to the nearest desired bit away from zero and when there is a value at the midpoint between two possible rounded values, the one with the larger magnitude is selected. For example, to round 01.0110 to a Fix_4_2, this yields 01.10, because 01.0110 is exactly between 01.01 and 01.10 and the latter is further from zero.

Overflow

Overflow errors occur when a value lies outside the representable range. For overflow the options are to Saturate to the largest positive/smallest negative value, to Wrap (for example, to discard bits to the left of the most significant representable bit), or to Flag as error (an overflow as a Simulink error) during simulation. Flag as error is a simulation-only feature. The hardware generated is the same as when Wrap is selected.

Implementation Tab

Parameters specific to the Implementation tab are as follows:

Interface Options
Interface
None
Implies that during HDL Netlist generation, this Vector Real Gateway In is translated as an Input Port at the top level.
AXI4-Lite
Implies that during HDL Netlist generation, an AXI4-Lite interface will be created, and this Vector Real Gateway In is mapped to one of the registers within the AXI4-Lite interface.
Auto assign address offset

If the Vector Real Gateway In is configured to be an AXI4-Lite interface, this option allows an address offset to be automatically assigned to the register within the AXI4-Lite interface that the Vector Real Gateway In is mapped to.

Address offset

If Auto assign address offset is not checked, then this entry box allows you to explicitly specify an address offset to use. Must be a multiple of 4.

Interface Name

If the Vector Real Gateway In is configured to be an AX4-Lite interface, assigns a unique name to this interface. This name can be used to differentiate between multiple AXI4-Lite interfaces in the design. When using the IP catalog flow, you can expect to see an interface in the IP that Model Composer creates with the name <design_name>_<interface_name>_ s_axi.

Important: The Interface Name must be composed of alphanumeric characters (lowercase alphabetic) or an underscore (_) only, and must begin with a lowercase alphabetic character. axi4_lite1 is acceptable, 1AXI4-Lite is not.
Description

Additional designer comments about this Vector Real Gateway In that is captured in the interface documentation.

Default value
Constraints
IOB Timing Constraint

In hardware, a Vector Real Gateway In is realized as a set of input/output buffers (IOBs). There are three ways to constrain the timing on IOBs. They are: None, Data Rate, and Data Rate, Set 'FAST' Attribute.

  • If None is selected, no timing constraints for the IOBs are put in the user constraint file produced by Model Composer. This means the paths from the IOBs to synchronous elements are not constrained.
  • If Data Rate is selected, the IOBs are constrained at the data rate at which the IOBs operate. The rate is determined by System Clock Period provided on the Model Composer Hub block and the sample rate of the Gateway relative to the other sample periods in the design.
  • If Data Rate, Set 'FAST' Attribute is selected, the constraints described above are produced. In addition, a FAST slew rate attribute is generated for each IOB. This reduces delay but increases noise and power consumption.
Specify IOB location constraints
Checking this option allows IOB location constraints and I/O standards to be specified.
IOB pad locations, e.g. {'MSB', ..., 'LSB'}
IOB pin locations can be specified as a cell array of strings in this edit box. The locations are package-specific.
IO Standards, e.g. {'MSB', ..., 'LSB'}
I/O standards can be specified as a cell array of strings in this edit box. The locations are package-specific.