When a design is compiled during code generation, Vitis Model Composer produces constraints that tell downstream tools how to process the design. This enables the tools to produce a higher quality implementation, and to do so using considerably less time. Constraints supply the following:
- The period to be used for the system clock.
- The speed, with respect to the system clock, at which various portions of the design must run.
- The pin locations at which ports should be placed.
- The speed at which ports must operate.
The system clock period (that is, the period of the fastest hardware clock in the design) can be specified in the Model Composer Hub block. Model Composer writes this period to the constraints file. Downstream tools use the period as a goal when implementing the design.