System Generator - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

Important: The System Generator token will be removed in a future release of Vitis Model Composer. Please consider updating your model to use the Vitis Model Composer Hub block.

The System Generator token serves as a control panel for controlling system and simulation parameters, and it is also used to invoke the code generator for netlisting. Every Simulink® model containing any element from the HDL Blockset must contain at least one System Generator token. Once a System Generator token is added to a model, it is possible to specify how code generation and simulation should be handled.

Token Parameters

The parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Compilation tab
Parameters specific to the Compilation tab are as follows.
Board

Specifies a Xilinx, Partner, or Custom board you will use to test your design. You can specify a Board for any of the compilation targets you select with the Compilation setting described below (IP Catalog, Hardware Co-Simulation, Synthesized Checkpoint, or HDL Netlist).

When you select a Board, the Part field displays the name of the Xilinx device on the selected Board, and this part name cannot be changed.

For a Partner board or a custom board to appear in the Board list, you must configure Model Composer to access the board files that describe the board.

Part
Defines the Xilinx FPGA or SoC part to be used. If you have selected a Board, the Part field will display the name of the Xilinx device on the selected Board, and this part name cannot be changed.
Compilation

Specifies the type of compilation result that should be produced when the code generator is invoked. The default compilation type is IP Catalog.

The Settings button is activated when one of these compilation types is selected:

IP Catalog compilation
The Settings button brings up a dialog box that allows you to add a description of the IP that will be placed in the IP catalog.
Hardware Co-Simulation (JTAG) compilation
The Settings button brings up a dialog box that allows you to use burst data transfers to speed up JTAG hardware co-simulation.
Hardware Description Language
Specifies the HDL language to be used for compilation of the design. The possibilities are VHDL and Verilog.
VHDL library
Specifies the name of VHDL work library for code generation. The default name is xil_defaultlib.
Use STD_LOGIC type for Boolean or 1 bit wide gateways
If your design's Hardware Description Language (HDL) is VHDL, selecting this option will declare a Boolean or 1-bit port (Gateway In or Gateway Out) as a STD-LOGIC type. If this option is not selected, Model Composer will interpret Boolean or 1-bit ports as vectors.
Note: When you enable this option and try to run Generate code and Run behavioral simulation in Vivado, you might see a failure during the elaboration phase.
Target directory
Defines where Model Composer should write compilation results. Because Model Composer and the FPGA physical design tools typically create many files, it is best to create a separate target directory, for example, a directory other than the directory containing your Simulink® model files.
Synthesis strategy
Choose a Synthesis strategy from the pre-defined strategies in the drop-down list.
Implementation strategy
Choose an Implementation strategy from the pre-defined strategies in the drop-down list.
Create interface document
When this box is checked and the Generate button is activated for netlisting, Model Composer creates an HTM document that describes the design being netlisted. This document is placed in a “documentation” subfolder under the netlist folder.

Adding Designer Comments to the Generated Document: If you want to add personalized comments to the auto-generated document, follow this procedure.

  1. As shown below, double click the Simulink canvas at the top level and add a comment that starts with Designer Comments:
    Figure 1. Designer Comments
  2. Double click the System Generator token, click the Create interface document box at the bottom of the Compilation tab, then click Generate.
  3. When netlisting is complete, navigate to the documentation subfolder underneath the netlist folder and double-click on the HTM document.

    Designer Comments section is created in the document and your personalized comments are included.

    Figure 2. Designer Comments Section
Create testbench
This instructs Model Composer to create an HDL test bench. Simulating the test bench in an HDL simulator compares Simulink simulation results with ones obtained from the compiled version of the design. To construct test vectors, Model Composer simulates the design in Simulink, and saves the values seen at gateways. The top HDL file for the test bench is named <name>_testbench.vhd / .v, where <name> is a name derived from the portion of the design being tested.
Note: Test bench generation is not supported for designs that have gateways (Gateway In or Gateway Out) configured as an AXI4-Lite Interface
Model Upgrade
Generates a Status Report that helps you identify and upgrade blocks that are not the latest available.
Clocking tab
Parameters specific to the Clocking tab are as follows.
Enable multiple clocks
Must be enabled in the top-level System Generator token of a multiple clock design. This indicates to the Code Generation engine that the clock information for the various Subsystems must be obtained from the System Generator tokens contained in those Subsystems. If not enabled, then the design will be treated as a single clock design where all the clock information is inherited from the top-level System Generator token.
FPGA clock period(ns)
Defines the period in nanoseconds of the system clock. The value need not be an integer. The period is passed to the Xilinx implementation tools through a constraints file, where it is used as the global PERIOD constraint. Multicycle paths are constrained to integer multiples of this value.
Clock pin location
Defines the pin location for the hardware clock. This information is passed to the Xilinx implementation tools through a constraints file. This option should not be specified if the Model Composer design is to be included as part of a larger HDL design.
Provide clock enable clear pin
This instructs Model Composer to provide a ce_clr port on the top-level clock wrapper. The ce_clr signal is used to reset the clock enable generation logic. Capability to reset clock enable generation logic allows designs to have dynamic control for specifying the beginning of data path sampling.
Simulink system period (sec)
Defines the Simulink System Period, in units of seconds. The Simulink system period is the greatest common divisor of the sample periods that appear in the model. These sample periods are set explicitly in the block dialog boxes, inherited according to Simulink propagation rules, or implied by a hardware oversampling rate in blocks with this option. In the latter case, the implied sample time is in fact faster than the observable simulation sample time for the block in Simulink. In hardware, a block having an oversampling rate greater than one processes its inputs at a faster rate than the data. For example, a sequential multiplier block with an over-sampling rate of eight implies a (Simulink) sample period that is one eighth of the multiplier block’s actual sample time in Simulink. This parameter can be modified only in a master block.
Perform analysis
Specifies whether an analysis (timing or resource) will or will not be performed on the Model Composer design when it is compiled. If None is selected, no timing analysis or resource analysis will be performed. If Post Synthesis is selected, the analysis will be performed after the design has been synthesized in the Vivado® toolset. If Post Implementation is selected, the analysis will be performed after the design is implemented in the Vivado toolset.
Analyzer type
Two selections are provided: Timing or Resource. After generation is completed, a Timing Analyzer table or Resource Analyzer table is launched.
Launch analyzer
Launches the Timing Analyzer or Resource Analyzer table, depending on the selection of Analyzer type. This will only work if you already ran analysis on the Simulink model and haven't changed the Simulink model since the last run.
General tab
Parameters specific to the General tab are as follows.
Block icon display
Specifies the type of information to be displayed on each block icon in the model after compilation is complete. The various display options are described below.
Default
Displays the default block icon information on each block in the model. A block’s default icon is derived from the xbsIndex library.
Figure 3. Default Block Icon
Normalized Sample Periods
Displays the normalized sample periods for all the input and output ports on each block. For example, if the Simulink System Period is set to 4 and the sample period propagated to a block port is 4 then the normalized period that is displayed for the block port is 1 and if the period propagated to the block port is 8 then the sample period displayed would be 2 for example, a larger number indicates a slower rate.
Figure 4. Normalized Sample Periods Icon
Sample frequencies (MHz)
Displays sample frequencies for each block.
Pipeline stages
Displays the latency information from the input ports of each block. The displayed pipeline stage might not be accurate for certain high-level blocks such as the FFT, RS Encoder/Decoder, Viterbi Decoder, etc. In this case the displayed pipeline information can be used to determine whether a block has a combinational path from the input to the output. For example, the Up Sample block in the figure below shows that it has a combinational path from the input to the output port.
Figure 5. Sample Frequencies
HDL port names
Displays the HDL port name of each port on each block in the model.
Input data types
Displays the data type of each input port on each block in the model.
Output data types
Displays the data type of each output port on each block in the model.
Remote IP cache
If selected, your design will access an IP cache whenever a Model Composer compilation performs Vivado synthesis as part of the compilation. If the compilation generates an IP instance for synthesis, and the Vivado synthesis tool generates synthesis output products, the tools create an entry in the cache area. If a new customization of the IP is created which has the exact same properties, the tools will copy the synthesis outputs from the cache to the design’s output directory instead of synthesizing the IP instance again. Accessing the disk cache speeds up the iterative design process.

IP caching is described in HDL Library.

Clear cache
Clicking this button clears the remote IP cache. Clearing the cache saves disk space, because the IP Cache can grow large, especially if your design uses many IP modules.