Step 2: Parse the BD File and Import Un-Located Ports and Interfaces into Model Composer - 2022.2 English

Vitis Model Composer User Guide (UG1483)

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2022.2 English

You can now use the xilinx.utilities.importBD utility in Vitis Model Composer to import the BD (Block Diagram) that you created in the Vivado® IP integrator.

This utility takes in the platform framework Vivado project and the name of the new model to be created in Model Composer. It parses the platform design for potential Model Composer ports and external interfaces (that is, interfaces whose ports do not have location attributes, based on the board connectivity and automation) and creates a sample stub in Model Composer representing the accelerator portion of the design.


xilinx.utilities.importBD takes in the platform Vivado project and the name of the new model to be created. It parses the platform for potential Model Composer ports and interfaces and creates a sample stub for the user to make development easy. If the new model name is not specified an untitled model will be opened.

Inputs are: The Vivado project and the model_name (optional)



<project_name>.xpr', 'mynewmodel') 


xilinx.utilities.importBD('C:\test_importBD\platform.xpr', 'mynewmodel')

In Model Composer, the resulting model will look like the example below.

Figure 1. Model Composer Model

The model in Model Composer will have these features:

  • For each AXI4-Lite interface, a Gateway In and a Gateway Out block will appear. You can then replicate and add as many AXI4-Lite gateways as your design requires.
  • For an AXI4-Stream interface, the associated TDATA, TVALID, TREADY, and other AXI4-Stream ports will appear.
  • The model’s Vitis Model Composer Hub block is set to a Compilation target of IP Catalog and the Part or Board will be set to the same Xilinx device or board as that of the Vivado project.