Setting the AIE to HDL Block - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

The following image depicts the components that are needed to connect an AI Engine subsystem to an HDL design. In setting this connection, you should consider certain input design criteria and set the parameters of the blocks accordingly. These input design criteria are:

  1. In the HDL design, the bit width of the tdata signal line (W). This is the bit width of the data in the programmable logic.
  2. HDL design sample time (T). This sample time determines the target clock rate for which the HDL design will be clocked in hardware. For single clock designs, this will be the sample time set in the Gateway In AXIS block.
  3. As mentioned previously, simulation in HDL domain is cycle-accurate. An HDL design might not be ready to accept a new sample at every cycle (the tready signal from the HDL design will be set to zero when the HDL design cannot accept new samples). This is referred as the initilization interval (II) of the HDL design. For example, if an HDL design accepts a new sample every 10 cycles, the design would have an ii of 10. A design that can accept a new sample at every clock cycle has an initiation interval of one.
  4. The number of samples in the output of the AI Engine kernel (S).
  5. The output data type of the AI Engine kernel (DT).

Set P to be the period of the AI Engine subsystem. Note that all the inputs and outputs signals of the AI Engine subsystem must have the same period. Later a lower limit will be determined for P.

Note: The PLIO block is a pass-through block and only impacts code generation.
Figure 1. Setting the AIE to HDL Block

Step 1: Set the PLIO bit width in the PLIO Block

Set the PLIO bit width to W.

Step 2: Set Parameters of the AIE to HDL Block

Output Data Type

Set the Output Data Type such that the output bit width is W. If W is larger than the bit width of the input, the output should be unsigned, or else the output should have the same signedness of the input. Note that the input bit width cannot be larger than W.

Output Sample Time

Set the Ouptut Sample Time to Inherit: Same as tready (this is equivalent of setting this to T). Note that the bit rate into the block is:



and the output bit rate of the block is:



For the internal buffers of the block not to overflow, the input rate should be less than or equal to the output rate. However, the HDL design has an initialization interval of ii. As such,

or

Step 3: Set parameters of the Gateway In AXI Stream block

  • Set Output data type to W.
  • Set Sample Time to T.