Performing Timing Analysis - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

Timing analysis can be invoked whenever you generate any of the following compilation targets:

  • IP catalog
  • Hardware Co-Simulation
  • Synthesized Checkpoint
  • HDL Netlist

To perform timing analysis in Vitis Model Composer:

  1. Double-click the Vitis Model Composer Hub block in the Simulink model.
  2. Enter the following in the Vitis Model Composer Hub dialog box:
    1. In the HDL Settings tab, specify a Code Directory.
    2. In the HDL Analysis tab, set the Perform Analysis field to Post Synthesis or Post Implementation based on the runtime versus accuracy tradeoff. Post Synthesis timing will be less accurate but run faster, while Post Implementation timing will be more accurate but run slower.
    3. In the HDL Analysis tab, set the Analysis Type field to Timing.


  3. In the Model Composer Hub dialog box, click Generate.

    When you generate, the following occurs:

    1. Model Composer generates the required files for the selected compilation target. For timing analysis Model Composer invokes Vivado in the background for the design project, and passes design timing constraints to Vivado.
    2. Depending on your selection for Perform Analysis (Post Synthesis or Post Implementation), the design runs in Vivado through synthesis or through implementation.
    3. After the Vivado tools run is completed, timing paths information is collected and saved in a specific file format from the Vivado timing database. At the end of the timing paths data collection the Vivado project is closed and control is passed to the MATLAB® /Model Composer process.
    4. Model Composer processes the timing information and displays a Timing Analyzer table with timing paths information (see below).


    In the timing analyzer table:

    • Only unique paths from the Simulink model are reported.
    • The 50 paths with the lowest Slack values are displayed with the worst Slack at the top, and increasing Slack below.
    • Paths with timing violations have a negative Slack and display in red.
    • The display order can be sorted for any column’s values by clicking the column head.
    • To show/hide columns, click the Select Columns button and select/deselect the column name as required.

    • For a design with multiple clock cycle constraints, the Timing Analyzer can identify multicycle path constraints, and show them in the Path Constraints column. In that case, the Source Clock, and Destination Clock columns display clock enable signals to reflect different sampling rates.

    • You can cross probe from the table to the Simulink model by selecting a path in the table, which will highlight the corresponding HDL blocks in the Simulink model. See Cross Probing from the Timing Analysis Results to the Model.