Performing Burst Mode Hardware Co-Simulation - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

To perform the burst mode hardware co-simulation, you will execute the MATLAB M-code test bench that was generated automatically during compilation (see Compiling a Model for Hardware Co-Simulation).

This test bench resides in the Target directory specified when the design was compiled for the hardware co-simulation compilation target.

The test bench is named as follows:

  • If you compiled the top-level design the test bench will be named:
    <design_name>_hwcosim_test.m
  • If you compiled a subsystem of the design the test bench will be named:
    <design_name>_<sub_system>_hwcosim_test.m
    Note: If your board contains a Zynq® SoC device, you must install the Vitis™ unified software platform with the Vivado® Design Suite to perform hardware co-simulation.

To perform burst mode hardware co-simulation, do the following:

  1. Set up the board for performing JTAG hardware co-simulation.
  2. Run the test bench script from the MATLAB console. To run the test bench script, you can open the MATLAB console, change directory to the Target directory and run the script by name.

    The script runs the Simulink model to determine the stimulus data driven to the Xilinx Gateway In blocks (from the other Simulink source blocks or MATLAB variables), and captures the expected output produced by the Xilinx block design (BD), and exports the data to the Target directory as these separate data files:

    <design_name>_<sub_system>_<port_name>.dat

    The test bench then compares actual to expected outputs.

    If the test fails this will be printed on the console, and the failing comparisons will be listed in this file:

    <design_name>_<sub_system>_hwcosim_test.result