Mapping to AXI4-Lite Interfaces - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
Release Date
2022.2 English

Gateway Ins and Gateway Outs that are tagged as AXI4-Lite registers are mapped to different 32-bit registers within a Memory Map as shown in the Schematic below.

The schematic below is an example of mapping to a single AXI4-Lite interface, assuming all gateways have the same interface name. In a schematic with multiple AXI4-Lite interfaces, for each group of gateways having the same interface name you would see a separate AXI4-Lite Interface.

Figure 1. Single AXI4-Lite Interface

As you can see in the diagram, a module called example_dds_inf_axi_lite_interface is inserted into the design RTL, and drives the config_tvalid and config_tdata ports of the Model Composer design. And at the top level, a slave AXI4-Lite Interface is exposed. It is within this module that address decoding is done and the config_tvalid and config_tdata ports are driven based on the address obtained from the processor.

The number of bits required for addressing (s_axi_araddr and s_axi_awaddr) is determined by the number of AXI4-Lite interface registers and the offset specifications of each AXI4-Lite register. Enough bits are provided during module generation to uniquely decode each register. In this example, there are two Gateways – phase_data and phase_valid. Each port is assigned an address offset of 0x0000 & 0x0004. Hence three address bits are allocated.