Known Issues - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

The following are some of the known issues:

  • The HWCosim Compilation Target is not supported for multiple clock designs.
  • Only FIFO and Dual Port RAM blocks can be in the top-level of the design when using multiple clocks.
  • The behavior of blocks that aid in the crossing of multiple clock domains is not cycle-accurate.
  • Unconnected or terminated output ports cannot be viewed in the Waveform Viewer.