Inverter - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

The Xilinx Inverter block calculates the bitwise logical complement of a fixed-point number. The block is implemented as a synthesizable VHDL module.

Block Parameters

The block parameters dialog box can be invoked by double-clicking the icon in your SimulinkĀ® model.

Other parameters used by this block are explained in the topic Common Options in Block Parameter Dialog Boxes.