Vitis™ Model Composer provides the HLS blockset in the Xilinx toolbox. This enables you to transform your algorithmic specifications to production-quality IP implementations using automatic optimizations and leveraging the high-level synthesis technology of Vitis HLS. Using the IP integrator in Vivado, you can then integrate the IP into a platform that, for example, might include a Zynq® device, DDR3 DRAM, and a software stack running on an Arm® processor.
The HLS library in the Xilinx Tool Box provides optimized blocks for use within the Simulink environment. These include basic functional blocks for expressing algorithms like Math, Linear Algebra, Logic, and Bit-wise operations and others.
The HLS library contains the following categories of elements.
| Library | Description |
|---|---|
| Logic and Bit Operations | Blocks that supports the compound logical operations and bit-wise operations. |
| Lookup Tables | Block set that performs a one dimensional lookup operation with an input index. |
| Math Functions | Blocks that implement mathematical functions. |
| Ports and Subsystems | Blocks that allow creation of subsystems and input/output ports. |
| Relational Operations | Block set to define some kind of relation between two entities (e.g., Numerical Equality and inequalities). |
| Signal Attributes | Includes block which helps to maintain the compatibility between input type and output type (e.g., Type casting). |
| Signal Operations | Blocks that support simple modifications to the time variable of the signal to generate new signals (e.g., Unit Delay). |
| Signal Routing | Blocks that supports the setup to track signal sources and destinations (e.g., Bus selector). |
| Sinks | Include blocks that receive physical signal output from other blocks. |
| Source | Include blocks that generate or import signal data. |
| Tools | Include blocks that controls the implementation/Interface of the Model. |
For information on specific blocks in the Model Composer HLS library, see HLS Blockset.
The HLS block library is compatible with the standard Simulink block library, and these blocks can be used together to create models that can be simulated in Simulink. However, only certain Simulink blocks are supported for code generation by Model Composer. The Simulink blocks compatible with output generation from Model Composer can be found in the HLS block library.
Model Composer also lets you create your own custom blocks from existing C/C++ code for use in models. Refer to Importing C/C++ Code as Custom Blocks for more information.
Your Model Composer design is bit-accurate with regard to the final implementation in hardware, though untimed. You can compile the design model into C++ code for synthesis in Vitis HLS, create HDL blocks, or create packaged IP to be used in Vivado.
To familiarize yourself with the Model Composer HLS library, the Vitis Model Composer Tutorial (UG1498) includes labs and data to walk you through the tool.
The rest of this document discusses the following topics: