Verification in Vitis Model Composer can be separated into two distinct processes:
- Verification of the algorithm in Simulink® to verify the functional correctness of the design.
- Verification of the Model Composer model, to confirm the equivalence of the simulation results in Simulink and the C++ and RTL outputs.
In high-level synthesis, running the compiled C program is referred to as C simulation. Executing the C++ algorithm generated by Model Composer simulates the function and verifies that the output from the code matches the output from the Simulink simulation to validate that the algorithm is functionally correct.
In C/RTL co-simulation, Vitis HLS uses the C test bench to simulate the C function prior to synthesis and to verify the RTL output. The verification process consists of three phases:
- The C simulation is executed and the inputs to the top-level subsystem are saved as “input vectors.”
- The input vectors are used in behavioral simulation of the RTL code for the top-level subsystem created by Vitis HLS. The outputs from the RTL are saved as “output vectors."
- The output vectors are applied to the C test bench as output from the top-level subsystem, to verify the results of the C-simulation match.
Vitis HLS uses this return value for both C simulation and C/RTL co-simulation to determine if the results are correct.