Introduction - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

The hardware validation flow for AI Engines and PL in Vitis Model Composer provides a methodology to verify AI Engine- and PL-based applications on Xilinx hardware (Versal devices). Vitis Model Composer provides the option to generate a hardware image targeting a specific platform for the Simulink model. This hardware image can then be run on a board to verify whether the results from hardware match with the simulation output. This image can be either baremetal or Linux-based. This section covers the details of the Hardware Validation flow.