Interconnecting AI Engine and HDL Blocks - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

The HDL blockset in the Xilinx® toolbox contains the common DSP building blocks such as adders, multipliers, and registers. It also includes a set of complex DSP building blocks such as FFTs, filters and memories. Model Composer automatically compiles designs into low-level representations (i.e., RTL) which can be targeted to programmable logic. The Versal hardware allows for connecting AI Engine kernels and PL kernels. However, HDL and AI Engine domains are incompatible in at least two aspects:

  • The HDL domain is cycle accurate, whereas the AI Engine domain is only bit accurate. A Model Composer HDL design might not be ready to accept input data or might not have a valid output and these are managed through tvalid and tready signals of AXI4-Streamports.
  • The HDL domain accepts only scalar inputs, whereas AI Engine blocks work with variable sized vector signals.

In order to properly manage the sampling times across two domains and simulate the heterogeneous system with both PL (modeled with HDL blocks) and AI Engine, Vitis Model Composer provides interface blocks in the Utilities library to connect from AI Engine to HDL blocks and vice-versa.

  • AIE to HDL - This block connects AI Engine to HDL blocks using an AXI4-Stream-like interface.
  • HDL to AIE - This block connects HDL to AI Engine blocks using an AXI4-Stream-like interface.

You can find these blocks in Xilinx Toolbox/Utilities/Connectors library.

Figure 1. Connector Blocks

As discussed, AIE to HDL and HDL to AIE blocks have tvalid and tready ports as depicted in the previous figure. The gateway from the AI Engine to the HDL domain can accept a vector input but generates a scalar output, meaning that in Simulink, the HDL domain will run at a different rate than the AI Engine domain. For example, if the AI Engine domain is producing 16 samples at every clock, the HDL domain must run at least 16 times faster to process the data. However, in some cases, the HDL domain needs to run even faster because the HDL domain, being a cycle accurate domain, might not consume one sample per clock. For example, if the HDL domain consumes one sample every two clocks (known as an initiation interval of 2), for the earlier example, the HDL domain needs to run 32 times faster than the AI Engine domain.

The following sections discuss setting the block parameters of the AIE to HDL and HDL to AIE blocks and includes examples.