Interconnect AI Engine and HLS Kernel Blocks - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

Connections between an output port of an AI Engine kernel and an input port of an HLS kernel use an AIE to HLS Kernel block. Connections between an output port of an HLS kernel and an input port of an AI Engine kernel use an HLS Kernel to AIE block. These blocks reformat the data to match the data type of the sink port. In this process no data (information) is lost; and it is simply adjusting the data type and the number of samples. For example, an interface block can reformat a signal carrying 64 int8 values to a signal carrying 16 int32 values. Use of these blocks are not mandatory if the data types between the HLS kernel block and the AI Engine blocks match.

These blocks are available in the Xilinx Toolbox/Utilites/Connectors library.