Insert Pipeline Registers - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

Insert pipeline registers wherever possible and reasonable. Deep pipelines are efficiently implemented with the Delay blocks because the SRL32 primitive is used. If an initial value is needed on a register, the Register block should be used. Also, if the input path of an SRL32 is failing timing, you should place a Register block before the related Delay block and reduce the latency of the Delay block by one. This allows the router more flexibility to place the Register and Delay block (SRL + Register) away from each other to maximize the margin for the routing delay of this path.

Figure 1. Pipeline Registers

As shown in the following figure, the Convert block can be pipelined with embedded register stages to guarantee maximum performance.

Figure 2. Convert Block

To achieve a more efficient implementation on some Xilinx blocks, you can select the Implement using behavioral HDL option. As shown below, if the delay on a Delay block is 32 or greater, Xilinx synthesis infers a SRLC32E (32-bit Shift-Register) which maps into a single LUT.

Figure 3. Implement Using Behavioral HDL

For block RAMs (BRAMs), use the internal output register. You do this by setting the latency from 1 (the default) to 2. This enables the block RAM output register.

When you are using DSP48E1s, use the input, output and internal registers; for FIFOs, use the embedded registers option. Also, check all the high-level IP blocks for pipelining options.