IP Instance Caching - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

For compilation targets that perform Vivado synthesis to generate their output products, Vitis Model Composer incorporates a disk cache to speed up the iterative design process.

With the cache enabled for your design, whenever your compilation generates an IP instance for synthesis, and the Vivado synthesis tool creates synthesis output products, the tools create an entry in the cache area.

After the cache is populated, when a new customization of the IP is created which has the exact same properties, the IP is not synthesized again; instead, the cache is referenced and the corresponding synthesis output in the cache is copied to your design's output directory. Because the IP instance is not synthesized again, and this process is repeated for every IP referenced in your design, generation of the output products is completed more quickly.

The following compilation targets invoke Vivado synthesis; these compilation targets will access the cache to synthesize IP in your design.

  • Hardware Co-Simulation
  • Synthesized Checkpoint

Also, when you compile your design and Perform analysis is selected for either Timing or Resource analysis, Vivado synthesis always runs, regardless of the compilation target. Because timing analysis or resource analysis can be performed several times for a design, enabling IP caching will improve overall performance. For a description of the Perform analysis compilation option, see Performing Timing Analysis or Performing Resource Analysis.

The IP cache is shared across multiple Simulink models on your system. If you reuse an IP in one design by including it in another design, and the IP is customized identically and has the same part and language settings in both Simulink models, you can gain the benefit of caching when you compile either of the designs.

To find the location of the IP cache directory on your system, enter the command xilinx.environment.getipcachepath on the MATLAB command line. The full path to the IP cache directory will display in the MATLAB command window.

>> xilinx.environment.getipcachepath
ans =
C:/Users/your_id/AppData/Local/Xilinx/Sysgen/SysgenVivado/win64.o/ip

IP caching in Model Composer is similar to IP caching in the Vivado Design Suite, described at this link in the Vivado Design Suite User Guide: Designing with IP (UG896). However, the IP cache for Model Composer designs is in a different location than the IP cache for Vivado projects.