Vitis Model Composer can compile designs into FPGA hardware that can be used in the loop with Simulink® simulations. This capability is discussed in the topic Using Hardware Co-Simulation.
As shown in the following figure, you can select Hardware Co-Simulation compilation by selecting it from the Compilation Type menu on the HDL Settings tab.
JTAG Hardware Co-Simulation is supported for all Xilinx development boards.
The Simulink library (<design_name>_hwcosim_lib.slx)
generated as part of a Hardware Co-Simulation compilation is placed in the
directory you specified in the Code
directory field. This library, and the hardware
co-simulation block stored in the library, are described in Hardware Co-Simulation Blocks.