## Basic Element Blocks

Block | Description |
---|---|

Absolute | The Xilinx Absolute block outputs the absolute value of the input. |

Accumulator | The Xilinx Accumulator block implements an adder or subtractor-based scaling accumulator. |

AddSub | The Xilinx AddSub block implements an adder/subtractor. The operation can be fixed (Addition or Subtraction) or changed dynamically under control of the sub mode signal. |

CMult | The Xilinx CMult block implements a gain operator, with output equal to the product of its input by a constant value. This value can be a MATLAB expression that evaluates to a constant. |

Convert | The Xilinx Convert block converts each input sample to a number of a desired arithmetic type. For example, a number can be converted to a signed (two's complement), or unsigned value. |

Depuncture | The Xilinx Depuncture block allows you to insert an arbitrary symbol into your input data at the location specified by the depuncture code. |

Divide | The Xilinx Divide block performs both fixed-point and floating-point division with the a input being the dividend and the b input the divisor. Both inputs must be of the same data type. |

Down Sample | The Xilinx Down Sample block reduces the sample rate at the point where the block is placed in your design. |

Exponential | This Xilinx Exponential block preforms the exponential operation on the input. Currently, only the floating-point data type is supported. |

Expression | The Xilinx Expression block performs a bitwise logical expression. |

Mult | The Xilinx Mult block implements a multiplier. It computes the product of the data on its two input ports, producing the result on its output port. |

MultAdd | The Xilinx MultAdd block performs both fixed-point and floating-point multiply and addition with the a and b inputs used for the multiplication and the c input for addition or subtraction. |

Mux | The Xilinx Mux block implements a multiplexer. The block has one select input (type unsigned), and a user-configurable number of data bus inputs, ranging from 2 to 1024. |

Natural Logarithm | The Xilinx Natural Logarithm block produces the natural logarithm of the input. |

Negate | The Xilinx Negate block computes the arithmetic negation of its input. |

Parallel to Serial | The Parallel to Serial block takes an input word and splits it into N time-multiplexed output words where N is the ratio of number of input bits to output bits. The order of the output can be either least significant bit first or most significant bit first. |

Puncture | The Xilinx Puncture block removes a set of user-specified bits from the input words of its data stream. |

Reciprocal | The Xilinx Reciprocal block performs the reciprocal on the input. Currently, only the floating-point data type is supported. |

Reciprocal SquareRoot | The Xilinx Reciprocal SquareRoot block performs the reciprocal squareroot on the input. Currently, only the floating-point data type is supported. |

Reinterpret | The Xilinx Reinterpret block forces its output to a new type without any regard for retaining the numerical value represented by the input. |

Relational | The Xilinx Relational block implements a comparator. |

Requantize | The Xilinx Requantize block requantizes and scales its input signals. |

Scale | The Xilinx Scale block scales its input by a power of two. The power can be either positive or negative. The block has one input and one output. The scale operation has the effect of moving the binary point without changing the bits in the container. |

Serial to Parallel | The Serial to Parallel block takes a series of inputs of any size and creates a single output of a specified multiple of that size. The input series can be ordered either with the most significant word first or the least significant word first. |

Shift | The Xilinx Shift block performs a left or right shift on the input signal. The result will have the same fixed-point container as that of the input. |

Slice | The Xilinx Slice block allows you to slice off a sequence of bits from your input data and create a new data value. This value is presented as the output from the block. The output data type is unsigned with its binary point at zero. |

SquareRoot | The Xilinx SquareRoot block performs the square root on the input. Currently, only the floating-point data type is supported. |

Threshold | The Xilinx Threshold block tests the sign of the input number. If the input number is negative, the output of the block is -1; otherwise, the output is 1. The output is a signed fixed-point integer that is 2 bits long. The block has one input and one output. |

Time Division Demultiplexer | The Xilinx Time Division Demultiplexer block accepts input serially and presents it to multiple outputs at a slower rate. |

Time Division Multiplexer | The Xilinx Time Division Multiplexer block multiplexes values presented at input ports into a single faster rate output stream. |

Up Sample | The Xilinx Up Sample block increases the sample rate at the point where the block is placed in your design. The output sample period is l/n, where l is the input sample period, and n is the sampling rate. |

## DSP Blocks

Block | Description |
---|---|

Digital FIR Filter | The Xilinx Digital FIR Filter block allows you to generate highly parameterizable, area-efficient, high-performance single channel FIR filters. |

DSP Macro 1.0 | The Xilinx DSP macro block provides a device independent abstraction of the DSP48E1, DSP48E2, and DSP58 blocks. Using this block instead of using a technology-specific DSP slice helps makes the design more portable between Xilinx technologies. |

DSP48E | The Xilinx DSP48E block is an efficient building block for DSP applications that use supported devices. The DSP48E combines an 18-bit by 25-bit signed multiplier with a 48-bit adder and programmable mux to select the adder's input. |

DSP48E1 | The Xilinx DSP48E1 block is an efficient building block for DSP applications that use 7 series devices. Enhancements to the DSP48E1 slice provide improved flexibility and utilization, improved efficiency of applications, reduced overall power consumption, and increased maximum frequency. The high performance allows designers to implement multiple slower operations in a single DSP48E1 slice using time-multiplexing methods. |

DSP48E2 | The Xilinx DSP48E2 block is an efficient building block for DSP applications that use UltraScale™ devices. DSP applications use many binary multipliers and accumulators that are best implemented in dedicated DSP resources. UltraScale™ devices have many dedicated low-power DSP slices, combining high speed with small size while retaining system design flexibility. |

DSP58 |
The Xilinx DSP58 block is an efficient building block for DSP applications that use Versal® devices. DSP applications use many binary multipliers and accumulators that are best implemented in dedicated DSP resources. Versal® devices have many dedicated low-power DSP slices, combining high speed with small size while retaining system design flexibility. |

DSPCPLX | The Xilinx DSPCPLX block is one of the advanced features provided by Versal® architecture DSP, which is the optimized solution to deal with 18x18 complex multiplication followed by 58 + 58 accumulation operation. |

FFT | The Xilinx FFT (Fast Fourier Transform) block takes a block of time domain waveform data and computes the frequency of the sinusoid signals that make up the waveform. |

Inverse FFT | The Xilinx Inverter FFT block performs a fast inverse (or backward) Fourier transform (IDFT), which undoes the process of Discrete Fourier Transform (DFT). The Inverter FFT maps the signal back from the frequency domain into the time domain. |

Product | The Xilinx Product block implements a scalar or complex multiplier. It computes the product of the data on its two input channels, producing the result on its output channel. For complex multiplication the input and output have two components: real and imaginary. |

Sine Wave | The Xilinx Sine Wave block generates a sine wave, using simulation time as the time source. |

CIC Compiler 4.0 | The Xilinx CIC Compiler provides the ability to design and implement AXI4-Stream-compliant Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices. |

Complex Multiplier 6.0 | The Complex Multiplier block implements AXI4-Stream compliant, high-performance, optimized complex multipliers for devices based on user-specified options. |

Convolution Encoder 9.0 | The Xilinx Convolution Encoder block implements an encoder for convolution codes. Ordinarily used in tandem with a Viterbi decoder, this block performs forward error correction (FEC) in digital communication systems. This block adheres to the AMBA AXI4-Stream standard. |

CORDIC 6.0 | The Xilinx CORDIC block implements a generalized coordinate rotational digital computer (CORDIC) algorithm and is AXI compliant. |

DDS Compiler 6.0 | The Xilinx DDS (Direct Digital Synthesizer) Compiler block implements high performance, optimized Phase Generation, and Phase to Sinusoid circuits with AXI4-Stream compliant interfaces for supported devices. |

Divider Generator 5.1 | The Xilinx Divider Generator block creates a circuit for integer division based on Radix-2 non-restoring division, or High-Radix division with prescaling. |

Fast Fourier Transform 9.1 | The Xilinx Fast Fourier Transform block implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the Discrete Fourier Transform (DFT). In addition, the block provides an AXI4-Stream-compliant interface. |

FIR Compiler 7.2 | This Xilinx FIR Compiler block provides users with a way to generate highly parameterizable, area-efficient, high-performance FIR filters with an AXI4-Stream-compliant interface. |

Interleaver/De-interleaver 8.0 | The Xilinx Interleaver Deinterleaver block implements an interleaver or a deinterleaver using an AXI4-compliant block interface. An interleaver is a device that rearranges the order of a sequence of input symbols. The term symbol is used to describe a collection of bits. In some applications, a symbol is a single bit. In others, a symbol is a bus. |

Reed-Solomon Decoder 9.0 | The Reed-Solomon (RS) codes are block-based error correcting codes with a wide range of applications in digital communications and storage. |

Reed-Solomon Encoder 9.0 | The Reed-Solomon (RS) codes are block-based error correcting codes with a wide range of applications in digital communications and storage. This block adheres to the AMBA® AXI4-Stream standard. |

Viterbi Decoder 9.1 | Data encoded with a convolution encoder can be decoded using the Xilinx Viterbi decoder block. This block adheres to the AMBA® AXI4-Stream standard. |

## Interface Blocks

Block | Description |
---|---|

Gateway In | The Xilinx Gateway In blocks are the inputs into the Xilinx portion of your Simulink design. These blocks convert Simulink integer, double, and fixed-point data types into the Model Composer fixed-point type. Each block defines a top-level input port or interface in the HDL design generated by Model Composer. |

Gateway In AXI Stream | A utility block that makes connecting between HDL and AI Engine domains easier by combining three HDL gateway blocks into one block. It is primarily used with the AI Engine to HDL block. |

Gateway Out | Xilinx Gateway Out blocks are the outputs from the Xilinx portion of your Simulink design. This block converts the Model Composer fixed-point or floating-point data type into a Simulink integer, single, double, or fixed-point data type. |

Gateway Out AXI Stream | A utility block that makes connecting between HDL and AI Engine domains easier by combining three HDL gateway blocks into one block. It is primarily used with the HDL to AI Engine block. |

## Logic and Bit Operation Blocks

Block | Description |
---|---|

Assert | The Xilinx Assert block is used to assert a rate and/or a type on a signal. This block has no cost in hardware and can be used to resolve rates and/or types in situations where designer intervention is required. |

BitBasher | The Xilinx BitBasher block performs slicing, concatenation, and augmentation of inputs attached to the block. |

Concat | The Xilinx Concat block performs a concatenation of n bit vectors represented by unsigned integer numbers, for example, n unsigned numbers with binary points at position zero. |

Inverter |
The Xilinx Inverter block calculates the bitwise logical complement of a fixed-point number. The block is implemented as a synthesizable VHDL module. |

Logical | The Xilinx Logical block performs bitwise logical operations on fixed-point numbers. Operands are zero padded and sign extended as necessary to make binary point positions coincide; then the logical operation is performed and the result is delivered at the output port. |

## Memory Blocks

Block | Description |
---|---|

Addressable Shift Register | The Xilinx Addressable Shift Register block is a variable-length shift register in which any register in the delay chain can be addressed and driven onto the output data port. |

Delay | The Xilinx Delay block implements a fixed delay of L cycles. |

Dual Port RAM | The Xilinx Dual Port RAM block implements a random access memory (RAM). Dual ports enable simultaneous access to the memory space at different sample rates using multiple data widths. |

FIFO | The Xilinx FIFO block implements an FIFO memory queue. |

LFSR | The Xilinx LFSR block implements a Linear Feedback Shift Register (LFSR). This block supports both the Galois and Fibonacci structures using either the XOR or XNOR gate and allows a re-loadable input to change the current value of the register at any time. The LFSR output and re-loadable input can be configured as either serial or parallel ports. |

Register | The Xilinx Register block models a D flip-flop-based register, having a latency of one sample period. |

ROM | The Xilinx ROM block is a single port read-only memory (ROM). |

Single Port RAM | The Xilinx Single Port RAM block implements a random access memory (RAM) with one data input and one data output port. |

AXI FIFO | The Xilinx AXI FIFO block implements a FIFO memory queue with an AXI-compatible block interface. |

## Signal Routing Blocks

Block | Description |
---|---|

Bus Creator | This block creates buses from input signals |

Bus Selector | This block selects signals from incoming buses |

From | This block accepts inputs from the Goto block |

Goto | This block passes block inputs to theFrom blocks |

## Source Blocks

Block | Description |
---|---|

Constant | The Xilinx Constant block generates a constant that can be a fixed-point value, a Boolean value, or a DSP48 instruction. This block is similar to the Simulink constant block, but can be used to directly drive the inputs on Xilinx blocks. |

Counter | The Xilinx Counter block implements a free-running or count-limited type of an up, down, or up/down counter. The counter output can be specified as a signed or unsigned fixed-point number. |

Opmode | The Xilinx Opmode block generates a constant that is a DSP48E, DSP48E1, or DSP48E2 instruction. It is is a 15-bit instruction for DSP48E, a 20-bit instruction for DSP48E1, and a 22-bit instruction for DSP48E2. The instruction consists of the opmode, carry-in, carry-in select, alumode, and (for DSP48E1 and DSP48E2) the inmode bits. |

Reset Generator | The Xilinx Reset Generator block captures the user's reset signal that is running at the system sample rate, and produces one or more downsampled reset signal(s) running at the rates specified on the block. |

## SSR Blocks

Block | Description |
---|---|

Vector Absolute | The Vector Absolute block outputs the absolute value of the input of vector type. |

Vector AddSub Fabric | The Vector Adder/Subtracter Fabric block supports the Addition/Subtraction operation forinputs of vector type. |

Vector Assert | The Vector Assert block asserts a user-defined sample rate and/or type on Vector inputs. |

Vector Concat | The Vector Concat block concatenates two or more inputs of type vector. The output is cast toan unsigned value with the binary point at zero. |

Vector Convert | The Vector Convert block supports Data Type Conversion feature for vector type inputs. |

Vector Down Sample | The Vector Down Sample block down samples input vector data. |

Vector Logical | The Vector Logical block supports logical operation for vector type inputs. |

Vector Mux | The Vector Multiplexer block supports the Multiplexing feature for input of vector types. |

Vector Real Mult | The Vector Real Multiplier block supports the multiplication feature for vector type inputs. |

Vector Reinterpret | The Vector Reinterpret block changes the vector input signal type without altering the binary representation. |

Vector Relational | The Vector Relational block implements comparator for vector inputs. |

Vector Slice | The Vector Slice block extracts a given range of bits from each sample of input vector and presents it at the output. |

Vector Up Sample | The Vector Up Sample block up samples input vector data. Inserted values can be zeros or copies of the most recent input sample. |

Vector Complex Mult | The Vector Complex Multiplier block supports multiplication of two complex input vectors. |

Vector DDFS | The Vector DDFS block generates Real and Imaginary vector output signals of desired frequency. |

Vector FFT | The Vector FFT block supports the FFT operation for vector type inputs. |

Vector FIR | The Vector FIR block supports FIR filtering for vector type inputs. |

Scalar2Vector | The Scalar2Vector block converts scalar type input to vector type output. |

Vector Real Gateway In | The Vector Real Gateway In block converts vector inputs of type Simulink® integer, single,double, and fixed-point to Xilinx fixed-point or floating-point data type. |

Vector Real Gateway Out | The Vector Real Gateway Out block converts Xilinx fixed-point or floating-point type vector inputs into vector outputs of type Simulink integer, single, double, or fixed-point. |

Vector2Scalar | The Vector2Scalar block converts vector type input to scalar type output. |

Vector Delay | The Vector Delay block supports delay operation on vector type inputs. |

Vector Delay Delta | The Vector Delay Delta Block delays each vector element differently based on the given latencyand delay latency values. |

Vector Register | The Vector Register block supports vector type inputs. |

Vector Constant | The Vector Constant Block generates vector constant values. |

## Tools Blocks

Block | Description |
---|---|

System Generator |
Important: The System Generator token
will be removed in a future release of Vitis Model Composer. Please consider updating
your model to use the Vitis Model Composer Hub block.
The System Generator token serves as a control panel for
controlling system and simulation parameters, and it is also used to
invoke the code generator for netlisting. Every Simulink model containing any
element from the HDL Blockset must contain at least one System Generator token. Once a System Generator token is added to a model, it is
possible to specify how code generation and simulation should be
handled. |

Clock Enable Probe | The Xilinx Clock Enable (CE) Probe provides a mechanism for extracting derived clock enable signals from Xilinx signals in Model Composer models. |

Clock Probe | The Xilinx Clock Probe generates a double-precision representation of a clock signal with a period equal to the Simulink system period. |

FDATool | The Xilinx FDATool block provides an interface to the FDATool software available as part of the MATLAB Signal Processing Toolbox. |

Indeterminate Probe | The output of the Xilinx Indeterminate Probe indicates whether the input data is indeterminate (MATLAB value NaN). An indeterminate data value corresponds to a VHDL indeterminate logic data value of 'X'. |

Questa | The HDL Black Box block provides a way to incorporate existing HDL files into a model. When the model is simulated, co-simulation can be used to allow black boxes to participate. The Questa HDL co-simulation block configures and controls co-simulation for one or several black boxes. |

Sample Time | The Sample Time block reports the normalized sample period of its input. A signal's normalized sample period is not equivalent to its Simulink absolute sample period. In hardware, this block is implemented as a constant. |

Vitis Model Composer Hub | The Vitis Model Composer Hub block controls the behavior of the Vitis Model Composer tool. |

## User-Defined Functions Blocks

Block | Description |
---|---|

Black Box | The HDL Black Box block provides a way to incorporate hardware description language (HDL) models into Model Composer. |

MCode | The Xilinx MCode block is a container for executing a user-supplied MATLAB® function within Simulink. A parameter on the block specifies the M-function name. The block executes the M-code to calculate block outputs during a Simulink simulation. The same code is translated in a straightforward way into equivalent behavioral VHDL/Verilog when hardware is generated. |

Vitis HLS | The Xilinx Vitis™ HLS block allows the functionality of a Vitis HLS design to be included in a Model Composer design. The Vitis HLS design can include C, C++, and System C design sources. |