HDL Blocks used to Create Asynchronous Clock Domains - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

To pass data between the src_domain and dest_domain Subsystems, you can use any one of the following logics:

  1. FIFO block
  2. Dual Port RAM block
  3. Register block
  4. Black Box block, which allows existing VHDL, Verilog, and EDIF to be brought into a design. For more information about Black Box utility, refer to Importing HDL Modules.

These blocks configure themselves to be either synchronous single clock blocks or multiple clock blocks based on their context in the design. In this design, the FIFO block is used to cross the clock domains as shown in the figure below.

Figure 1. Cross Domain FIFO Block

To complete the design, the FIFO block at the top level of the design is included to enable Code Generation.