Grouping Blocks within a Clock Domain - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

Blocks are grouped together in Vitis Model Composer by using a Subsystem. Subsystems can also be used to group blocks within a clock domain. Clock settings for each subsystem can then be controlled by enabling multiple clocks on the HDL Clock Settings tab of the Vitis Model Composer Hub block.

Figure 1. Source Clock Domain

In the previous figure, a clock domain Subsystem called src_domain has been created. On the HDL Clock Settings tab, the FPGA clock period has been set to (1000/368) ns (368 MHz) and the Simulink system period to 1 sec. This implies that an advance of 1 Simulink second corresponds to (1000/368) ns of FPGA clock.

Similarly, another group of blocks representing another clock domain is included in a Subsystem called dest_domain. This Subsystem is configured to run at an FPGA clock period of 1000/245 ns (245 MHz). The Simulink system period is set to 368/245. This is done because the Simulink system period of the src_domain Subsystem is set to 1. Hence, you normalize the System period from the faster src_domain.

Figure 2. Destination Clock Domain