Gateway Out - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

Xilinx Gateway Out blocks are the outputs from the HDL portion of your Simulink® design. This block converts the Model Composer fixed-point or floating-point data type into a Simulink integer, single, double or fixed-point data type.

According to its configuration, the Gateway Out block can either define an output port for the top level of the HDL design generated by Model Composer, or be used simply as a test point that is trimmed from the hardware representation

Gateway Blocks

As listed below, the Xilinx Gateway Out block is used to provide the following functions:

  • Convert data from a Model Composer fixed-point or floating-point data type into a Simulink integer, single, double, or fixed-point data type.
  • Define I/O ports for the top level of the HDL design generated by Model Composer. A Gateway Out block defines a top-level output port.
  • Define test bench result vectors when the Model Composer Create Testbench box is checked. In this case, during HDL code generation, the outputs from the block that occur during Simulink simulation are logged as logic vectors in a data file. For each top level port, an HDL component is inserted in the top-level test bench that checks this vector against expected results during HDL simulation.
  • Name the corresponding output port on the top-level HDL entity.

Block Parameters

Basic tab
Parameters specific to the Basic tab are as follows.
Propagate data type to output
This option is useful when you instantiate a Model Composer design as a sub-system into a Simulink design. Instead of using a Simulink double as the output data type by default, the Model Composer data type is propagated to an appropriate Simulink data type according to the following table:
Table 1. Propagate Data Type Output
Model Composer Data Type Simulink Data Type
XFloat_8_24 single
XFloat_11_53 double
Custom floating-point precision data type exponent width and fraction width less than those for single precision single
Custom floating-point precision data type with exponent width or fraction width greater than that for single precision double
XFix_<width>_<binpt> sfix<width>_EN<binpt>
UFix_<width>_<binpt> ufix<width>_EN<binpt>
XFix_<width>_0 where width is 8, 16 or 32 int<width> where width is 8, 16 or 32
UFix_<width>_0 where width is 8, 16 or 32 uint<width> where width is 8, 16 or 32
XFix_<width>_0 where width is other than 8, 16 or 32 sfix<width>
UFix_<width>_0 where width is other than 8, 16 or 32 ufix<width>
Translate into Output Port
Having this box unchecked prevents the gateway from becoming an actual output port when translated into hardware. This checkbox is on by default, enabling the output port. When this option is not selected, the Gateway Out block is used only during debugging, where its purpose is to communicate with Simulink Sink blocks for probing portions of the design. In this case, the Gateway Out block will turn gray in color, indicating that the gateway will not be translated into an output port.
Implementation tab
Parameters specific to the Implementation tab are as follows.
Interface Options
Interface
None
During HDL Netlist generation, this Gateway Out will be translated as an Output Port at the top level.
AXI4-Lite
During HDL Netlist Generation, an AXI4-Lite interface will be created and the Gateway Out will be mapped to one of the registers within the AXI4-Lite interface.
Interrupt
During an IP catalog generation, this Gateway Out will be tagged as an Interrupt output port when the Model Composer design is packaged into an IP module that can be included in the Vivado® IP catalog.
Auto assign address offset
If a Gateway Out is configured to be an AXI4-Lite interface, this option allows an address offset to be automatically assigned to the register within the AXI4-Lite interface that the Gateway Out is mapped to.
Address offset
If Auto assign address offset is not checked, then this entry box allows you to explicitly specify a address offset to use. Must be a multiple of 4.
Interface Name
If the Gateway Out is configured to be an AXI4-Lite interface, assigns a unique name to this interface. This name can be used to differentiate between multiple AXI4-Lite interfaces in the design. When using the IP catalog flow, you can expect to see an interface in the IP that Model Composer creates with the name <design_name>_<interface_name>_ s_axi.
Important: The Interface Name must be composed of alphanumeric characters (lowercase alphabetic) or an underscore (_) only, and must begin with a lowercase alphabetic character. axi4_lite1 is acceptable, 1Axi4-Lite is not.
Description
Additional designer comments about this Gateway Out that is captured in the interface documentation.
Constraints
IOB Timing Constraint
In hardware, a Gateway Out is realized as a set of input/output buffers (IOBs). There are three ways to constrain the timing on IOBs. They are None, Data Rate, and Data Rate, Set 'FAST' Attribute.

If None is selected, no timing constraints for the IOBs are put in the user constraint file produced by Model Composer. This means the paths from the IOBs to synchronous elements are not constrained.

If Data Rate is selected, the IOBs are constrained at the data rate at which the IOBs operate. The rate is determined by System Clock Period provided on the Model Composer Hub block and the sample rate of the Gateway relative to the other sample periods in the design. For example, the following OFFSET = OUT constraints are generated for a Gateway Out named 'Dout' that is running at the system period of 10 ns:


# Offset out constraints 
NET "Dout(0)" OFFSET = OUT : 10.0 : AFTER "clk"; 
NET "Dout(1)" OFFSET = OUT : 10.0 : AFTER "clk"; 
NET "Dout(2)" OFFSET = OUT : 10.0 : AFTER "clk";

If Data Rate, Set 'FAST' Attribute is selected, the OFFSET = OUT constraints described above are produced. In addition, a FAST slew rate attribute is generated for each IOB. This reduces delay but increases noise and power consumption. For the previous example, the following additional attributes are added to the constraints file.


NET "Dout(0)" FAST; 
NET "Dout(1)" FAST; 
NET "Dout(2)" FAST; 
Specify IOB Location Constraints
Checking this option allows IOB location constraints to be specified.
IOB Pad Locations, e.g. {'MSB', ..., 'LSB'}
IOB pin locations can be specified as a cell array of strings in this edit box. The locations are package-specific.

Other parameters used by this block are explained in the topic Common Options in Block Parameter Dialog Boxes.