Gateway In AXI Stream - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English


Library

HDL/Interfaces

Description

This is a utility block that makes connecting between HDL and AI Engine domains easier by combining three HDL gateway blocks into one block. It is primarily used with the AIE to HDL block.
Note: The block name will be used as the AXIS name. The following figure shows how the block is used.
Figure 1. Gateway In AXI Usage

Parameters

Output Data Type
The output data type of the block. The output data type should match the receiving HDL design input.
Sample Time
The output sample time. Refer to the AIE to HDL block help to learn more how to set this parameter.