Design Considerations - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English
  • For designs with HDL blocks, the HDL Netlist generation directory must be ./netlist, and the sequence of code generation must be followed.
  • Designs with HLS kernel blocks connected to other HLS kernel blocks are not currently supported. Designs with HLS kernel blocks connected to AIE DUT are supported; however, you can connect multiple HLS kernels to the AIE DUT. For example, consider the topology as shown in the following figure.

    Here, two HLS kernels are connected to the different ports of the aie_sub. This is supported for the hardware validation flow.

  • HLS kernels must have AXI input and output ports.
  • You can only use HLS kernel blocks to import C/C++ code (for PL) and to connect with AI Engines. The blocks from the HLS library are not allowed to connect and co-simulate.