Debugging Multiple Clock Domain Signals - 2022.2 English

Vitis Model Composer User Guide (UG1483)

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2022.2 English

In Vitis Model Composer you can use cross probing between the signal in the Xilinx Waveform Viewer and the Simulink diagram to aid the debugging process.

To add a signal to the Waveform viewer, right-click the signal in the model and select Xilinx Add To Viewer. Simulating the design should launch the Waveform Viewer as shown below.

Figure 1. Waveform Viewer

All signals in same clock domain are colored similarly. In the figure above: src_domain/Slice/Out1 and dest_domain/Relational/Out1 are in different clock domains.