Burst Data Transfers for Hardware Co-Simulation - 2022.2 English

Vitis Model Composer User Guide (UG1483)

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2022.2 English

Hardware co-simulation (HWCosim) is a methodology by which a user can offload, either partially or whole, the most compute intensive portion of a model into the actual target FPGA platform. The host system provides the stimulus to the model via the co-simulation interface (typically JTAG) and post-processes the response. This methodology is useful for validating the correctness of the generated hardware design on the target platform itself, as well as for speeding up the simulation time during verification of the model in a hardware co-verification scenario.

MATLAB/Simulink in conjunction with Vitis Model Composer currently supports two variants of HWCosim: GUI-based and MATLAB M-script-based. The first is run under the control of the Simulink scheduler, and can only progress one clock cycle at a time, due to the potential for feedback loops in the model.

The second variant is MATLAB M-script based simulation under Model Composer control (M-HWCosim), which is commonly used in testbenches produced as collateral during the bitstream generation from the Model Composer Hub block. These testbenches are typically feedback-free and come with a-priori known input that can be transferred to the device in larger batches.