Black Box VHDL Library Support - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

This Black Box feature allows you to import VHDL modules that have predefined library dependencies. The following example illustrates how to do this import.

The VHDL module below is a 4-bit, Up counter with asynchronous clear (async_counter.vhd). It will be compiled into a library named async_counter_lib.



The VHDL module below is a 4-bit, Up counter with synchronous clear (sync_counter.vhd). It will be compiled into a library named sync_counter_lib.



The VHDL module below is the top-level module that is used to instantiate the previous modules. This is the module that you need to point to when adding the Black Box into your Model Composer model.



The VHDL is imported by first importing the top-level entity, top_level, using the Black Box.

Once the file is imported, the associated Black Box Configuration M-file needs to be modified as follows:



The interface function addFileToLibrary is used to specify a library name other than “work” and to instruct the tool to compile the associated HDL source to the specified library.

The Model Composer model should look similar to the following figure.

Figure 1. Model Composer Model with Black Box Support

The next step is to double-click the Model Composer Hub block and click the Generate button to generate the HDL netlist.

During the generation process, a Vivado IDE project (.xpr) is created and placed with the hdl_netlist folder under the netlist folder. If you double-click the Vivado IDE project and select the Libraries tab under the Source view, you will see not only a work library, but an async_counter_lib library and sync_counter_lib library as well.