Address Generation - 2022.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2023-01-13
Version
2022.2 English

The following assumptions are made in the automatic address-generation process:

  1. Each AXI4-Lite gateway is associated with a unique address offset that is aligned with a 32-bit word boundary (i.e., will be a multiple of 4).
  2. Addressing begins at zero.
  3. Addressing is incrementally assigned in the lexicographical order of the gateways. In the event two gateways have the same name - disambiguation will be arbitrary.
  4. All AXI4-Lite gateways must be less than 32-bits wide else an error is issued.
  5. If an AXI4-Lite gateway is less than 32-bits wide, then from the internal register, LSBs will be assigned into the Design Under Test (DUT).
  6. The following criteria is used to manage the user-specified offset addresses:
    1. All user-specified addresses are allocated to AXI4-Lite gateways before automatic allocation.
    2. If two user-specified addresses are the same, an error is issued only during generation (otherwise it will be ignored).
    3. If the remaining AXI4-Lite gateways that are set to allocate address automatically, Model Composer attempts to fill the "holes" left behind by user-specified addressing.