An AI Engine
kernel written using specialized intrinsic and imported into Vitis
Model Composer can be used as part of a larger
Versal®
ACAP system design. In addition to kernels operating on the AI Engines, you can specify kernels to run on the programmable logic (PL)
region of the device. The PL kernels can be written using RTL or HLS C/C++ functions.
The connection between AI Engine and the PL block is
routed through a physical channel interface tile and conceptually the data width of the
connections are 32 bits, 64 bits or 128 bits.
Model Composer allows connecting an AI Engine kernel to a HLS PL kernel only if the data types and complexities of these port matches. If the datatypes or complexities of the port of the AI Engine kernel and the port of the PL kernel do not match, an interface blocks should be used to reconcile the discrepancy.
This chapter discusses interconnecting HDL blocks or HLS C/C++ functions with AI Engine kernels: