The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/16/2022 Version 2022.2 | |
| Simulation Flows | Added Supported Simulation Models for Versal ACAP Blocks table. |
| AI Engine Simulation | Added information on AXI traffic generators. |
| Hardware Emulation | Added information on AXI traffic generators. |
| CIPS Verification IP | Added new section. |
| Using Incremental Implementation | Added new section. |
| Using Soft SLR Floorplan Constraints | Added new section. |
| Using SLR Crossing Registers | Added new section. |
| Clustering Logic | Added new section. |
| Estimating Power Throughout the Flow | Added Power Design Manager tool references. |
| Reviewing the Design Power Distribution After Running Power Analysis | Added Power Design Manager tool references. |
| Analyzing PL Kernel Performance in Simulation | Added more information on RTL kernel simulation. |
| Creating the Device Image | Added new section. |
| 05/25/2022 Version 2022.1 | |
| HLS Simulation | Added C simulation and Co-simulation description and updated UG1399 link. |
| NoC Simulation | Updated NoC AXI Traffic Generator GitHub link. |
| Methodology DRCs with Impact on Timing Closure | Added TIMING-56 check description. |
| Methodology DRCs with Impact on Signoff Quality and Hardware Stability | Added TIMING-54 to 57 check descriptions. |
| Balance SLR Utilization for SSI Devices | Added section. |
| Overconstraining the Design | Added overconstrain warning note. |
| SSI Technology Considerations | Added section. |
| Using Intelligent Design Runs | Added section. |
| Improving Performance in the PS | Added support to access Performance Monitor Units in the PS and NoC. |
| Improving Performance in the AI Engine | Added AI Engine APIs versus Intrinsics section. |